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### Verilog Interview Questions - 2

1. Given the following Verilog code, what value of "a" is displayed?
always @(clk)
begin
a = 0;
a < = 1;
\$display(a);
end
Answer

2. What is the difference between a = #10 b; and #10 a = b; ?
Answer

3. Let "a" be a 3 bit reg value.
initial
begin
a < = 3'b101;
a = #5 3'b000;
a < = #10 3'b111;
a < = #30 3'b011;
a = #20 3'b010;
a < = #5 3'b110;
end
What will be the value of "a" at time 0,5,10,... units till 40 units of time?
Answer

4. Write a verilog code to swap contents of two registers with and without using a temporary register.
Answer

5. What is the difference between:
c = check ? a : b; and
if(check) c = a;
else c = b;
Answer

6. What does `timescale 1 ns/ 1 ps’ signify in a verilog code?
Answer

7. what is the use of defparam?
Answer

8. What is a sensitivity list?
Answer

9. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity list? If yes, why? If not, why?
Answer

10. How to generate sine wave using verilog coding style?
Answer

### Digital Design Interview Questions - All in 1

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)?
Answer

2. Implement an 2-input AND gate using a 2x1 mux.
Answer

3. What is a multiplexer?
Answer

A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output.

4. What is a ring counter?
Answer

A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on.

5. Compare and Contrast Synchronous and Asynchronous reset.
Answer

Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for small reset gl…

### Gate-Level Modeling

>> Introduction
>> Gate Primitives
>> Delays
>> Examples

Introduction

In Verilog HDL a module can be defined using various levels of abstraction. There are four levels of abstraction in verilog. They are:
Behavioral or algorithmic level: This is the highest level of abstraction. A module can be implemented in terms of the design algorithm. The designer no need to have any knowledge of hardware implementation.Data flow level: In this level the module is designed by specifying the data flow. Designer must how data flows between various registers of the design.Gate level: The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design.Switch level: This is the lowest level of abstraction. The design is implemented using switches/transistors. Designer requires the knowledge of switch-level implementation details.
Gate-level modeling is virtually the lowest-level of abstraction, because t…

### Synchronous Reset vs. Asynchronous Reset

Why Reset?

A Reset is required to initialize a hardware design for system operation and to force an ASIC into a known state for simulation.

A reset simply changes the state of the device/design/ASIC to a user/designer defined state. There are two types of reset, what are they? As you can guess them, they are Synchronous reset and Asynchronous reset.

Synchronous Reset

A synchronous reset signal will only affect or reset the state of the flip-flop on the active edge of the clock. The reset signal is applied as is any other input to the state machine.

Advantages:
The advantage to this type of topology is that the reset presented to all functional flip-flops is fully synchronous to the clock and will always meet the reset recovery time.Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant…