1. What are the differences between a flip-flop and a latch?
Flip-flops are edge-sensitive devices where as latches are level sensitive devices.
Flip-flops are immune to glitches where are latches are sensitive to glitches.
Latches require less number of gates (and hence less power) than flip-flops.
Latches are faster than flip-flops.
2. What is the difference between Mealy and Moore FSM?
Mealy FSM uses only input actions, i.e. output depends on input and state. The use of a Mealy FSM leads often to a reduction of the number of states.
Moore FSM uses only entry actions, i.e. output depends only on the state. The advantage of the Moore model is a simplification of the behavior.
3. What are various types of state encoding techniques? Explain them.
One-Hot encoding: Each state is represented by a bit flip-flop). If there are four states then it requires four bits (four flip-flops) to represent the current state. The valid state values are 1000, 0100, 0010, and 0001. If the value is 0100, then it means second state is the current state.
One-Cold encoding: Same as one-hot encoding except that '0' is the valid value. If there are four states then it requires four bits (four flip-flops) to represent the current state. The valid state values are 0111, 1011, 1101, and 1110.
Binary encoding: Each state is represented by a binary code. A FSM having '2 power N' states requires only N flip-flops.
Gray encoding: Each state is represented by a Gray code. A FSM having '2 power N' states requires only N flip-flops.
4. Define Clock Skew , Negative Clock Skew, Positive Clock Skew.
Clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock.
There are two types of clock skew: negative skew and positive skew. Positive skew occurs when the clock reaches the receiving register later than it reaches the register sending data to the receiving register. Negative skew is the opposite: the receiving register gets the clock earlier than the sending register.
5. Give the transistor level circuit of a CMOS NAND gate.
6. Design a 4-bit comparator circuit.
7. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR (without inverting the output)?
8. Define Metastability.
If there are setup and hold time violations in any sequential circuit, it enters a state where its output is unpredictable, this state is known as metastable state or quasi stable state, at the end of metastable state, the flip-flop settles down to either logic high or logic low. This whole process is known as metastability.
9. Compare and contrast between 1's complement and 2's complement notation.
The only advantage of 1's complement is that it can be calculated easily, just by changing 0's into 1's and 1's into 0's. The 2's complement is calculated in two ways, (i) add 1 to the 1's complement of the number, and (ii) leave all the leading 0s in the least significant positions and keep first 1 unchanged, and then change 0's into 1's and 1's into 0's.
The advantages of 2's complement over 1's complement are:
(i) For subtraction with complements, 2's complement requires only one addition operation, where as for 1's complement requires two addition operations if there is an end carry.
(ii) 1's complement has two arithmetic zeros, all 0's and all 1's.
10. Give the transistor level circuit of CMOS, nMOS, pMOS, and TTL inverter gate.