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VLSI Interview Questions - 4

1. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?
Answer

2. What are static and dynamic power dissipation w.r.t to CMOS gate?
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3. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) considering Channel Length Modulation.
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4. Which is fastest among the following technologies: CMOS, BiCMOS, TTL, ECL?
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5. What is a transmission gate, and what is its typical use in VLSI?
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6. Draw the cross section of nMOS or pMOS.
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7. What should be done to the size of a pMOS transistor inorder to increase its threshold voltage?
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8. Explain the various MOSFET Capacitances and their significance.
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9. On what factors does the resistance of metal depend on?
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10. Draw the layout a CMOS NAND gate.
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Digital Design Interview Questions - All in 1

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Setup and Hold TIme

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In the above figure, the shaded region is the restricted region. The shaded region is divided into two parts by the dashed line. The left hand side part of shaded region is the setup time period and the right hand side part is the hold time…

Gate-Level Modeling

>> Introduction
>> Gate Primitives
>> Delays
>> Examples


Introduction

In Verilog HDL a module can be defined using various levels of abstraction. There are four levels of abstraction in verilog. They are:
Behavioral or algorithmic level: This is the highest level of abstraction. A module can be implemented in terms of the design algorithm. The designer no need to have any knowledge of hardware implementation.Data flow level: In this level the module is designed by specifying the data flow. Designer must how data flows between various registers of the design.Gate level: The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design.Switch level: This is the lowest level of abstraction. The design is implemented using switches/transistors. Designer requires the knowledge of switch-level implementation details.
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