Setup and Hold TIme

Every flip-flop has restrictive time regions around the active clock edge in which input should not change. We call them restrictive because any change in the input in this regions the output may be the expected one (*see below). It may be derived from either the old input, the new input, or even in between the two. Here we define, two very important terms in the digital clocking. Setup and Hold time.

  • The setup time is the interval before the clock where the data must be held stable.
  • The hold time is the interval after the clock where the data must be held stable. Hold time can be negative, which means the data can change slightly before the clock edge and still be properly captured. Most of the current day flip-flops has zero or negative hold time.


In the above figure, the shaded region is the restricted region. The shaded region is divided into two parts by the dashed line. The left hand side part of shaded region is the setup time period and the right hand side part is the hold time period. If the data changes in this region, as shown the figure. The output may, follow the input, or many not follow the input, or may go to metastable state (where output cannot be recognized as either logic low or logic high, the entire process is known as metastability).


The above figure shows the restricted region (shaded region) for a flip-flop whose hold time is negative. The following diagram illustrates the restricted region of a D flip-flop. D is the input, Q is the output, and clock is the clock signal. If D changes in the restricted region, the flip-flop may not behave as expected, means Q is unpredictable.


To avoid setup time violations:
  • The combinational logic between the flip-flops should be optimized to get minimum delay.
  • Redesign the flip-flops to get lesser setup time.
  • Tweak launch flip-flop to have better slew at the clock pin, this will make launch flip-flop to be fast there by helping fixing setup violations.
  • Play with clock skew (useful skews).
To avoid hold time violations:
  • By adding delays (using buffers).
  • One can add lockup-latches (in cases where the hold time requirement is very huge, basically to avoid data slip).
* may be expected one: which means output is not sure, it may be the one you expect. You can also say "may not be expected one". "may" implies uncertainty. Thanks for the readers for their comments.

15 Comments:

Anonymous said...

thanks for that, very simple to understand

sudheer said...

i didnot understand about negative hold time,example if the setup time is from 10.5 to 11ns at 11ns clock posedge is triggered so if the flip flop has negative hold time of -.1ns then it is equivalent to saying that setup time is .4 ns instead of .5ns ie the setup time can start from 10.6ns instead of 10.5 and hold time be set to 0ns

sathish kumar said...

good article...please check the following sentence in the first paragraph "We call them restrictive because any change in the input in this regions the output may be the expected one." I think NOT is missing.

Also the third point regarding avoiding setup violations what is slew? did you mean skew or slew rate?

Anonymous said...

NOT is not required

Anoop said...

yes i think Not is very much required else the concept is confusing.
Moreover,regarding another comment on slew or skew.In this context indeed its slew that means how fast the o/p changes w.r.t to change in i/p.

Anonymous said...

thanks for clarification, i didnt have idea about setup and hold time, these are very usefull for FPGA designers

Anonymous said...

you can also check the following link..
http://vlsi-expert.blogspot.com/2011/04/static-timing-analysis-sta-basic-part3a.html

Anonymous said...

yeah, there should be a not in the sentence.

Maruti Kakarla said...

Thanx, Can u give examples to relavent to the negative hold time

Anonymous said...

good one

tech knight said...

Really nice explanation! Simple and to the point!

...but the symbol that you have for your blog is masonic...

Anonymous said...

since hold time is the time where data shld remain constant after clk edge then hw does the concept of negative hold time justify??? since it is mentioned that negative hold time means, if input varies before clk edge & still be captured!!!

hold tym comes into consideration only AFTER clock edge rite???

dxVxb said...

Good. THank you .

reethu said...

can someone explain me why do some D-flipflops have a negative value for hold time?

vivek dadi said...

should the setup and hold value should be of ratio maintained...or it can be independent


and also should it have difference to be maintained

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