Hello... Welcome to the new Only-VLSI . Stay tuned for new and useful content in the field of VLSI. So please hit that subscribe button now, and sign up for email notifications. Thanks.
SystemVerilog SystemVerilog is a combined hardware description language (HDL) and hardware verification language (HVL) based on extensions to Verilog HDL. SystemVerilog as a RTL design language is an extension of Verilog HDL containing all features of Verilog. As a verification language SystemVerilog uses object-oriented programming (OOP) techniques similar to that of C++, Java etc. Clearly, the main advantage of SystemVerilog is the unification of HDL and HVL, that provides a single platform for RTL design and verification. As a HDL SystemVerilog supports C/C++ like features including typedef, struct, union, enum, etc. These new features can be used for faster and efficient implementation of HDL, increasing the productivity of RTL design process. However, SystemVerilog’s strongest suite comes as a HVL. It provides a complete verification environment supporting constraint random generation, assertion based verification and coverage driven verification. Some of the SystemVerilo