### Type-1: Design a ...

Most Common Interview Questions: Type-1: Design a ...

This is the most common question one will face in his/her interview, probably the first question which starts testing your knowledge. (I mean this comes after introduction and "Tell us about yourself"). This is a lethal weapon used by the interviewer to test one's abilities: both weak and strong points. The concepts required for solving the problem are generally related to the type of job you are being tested for.

The most popular strategy used by the interview in this question is gradual increase in the complexity of the question. It goes like this ... Interviewer states the specifications of the design. You can present as simple/straight forward/redundant answer as possible. The next question could be redesign using only NOR gates or NAND gates. Followed by "what are minimum number of NAND gates required for this particular design" and it goes on.

Sometimes it starts with designing a small block. Then you will be asked to embed this module in a bigger picture and analyze the scenario. Where most likely you will face questions like "can the design (you made) be optimized for better performance of the entire module?" or "what drawbacks you see in your design when embedded in the bigger module". Basically tests how good you are with designs with a hierarchy.

Another way is step by step removal of assumptions that make the design complex as we go further.

Tips
• Read the job description, think of possible questions or target areas, and prepare for the same.
• ASIC interviews (especially freshers) expect a question dealing timing analysis, synthesis related issues, etc.

### Popular posts from this blog

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)?

2. Implement an 2-input AND gate using a 2x1 mux.

3. What is a multiplexer?

A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output.

4. What is a ring counter?

A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on.

5. Compare and Contrast Synchronous and Asynchronous reset.

Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for small reset gl…

### Gate-Level Modeling

>> Introduction
>> Gate Primitives
>> Delays
>> Examples

Introduction

In Verilog HDL a module can be defined using various levels of abstraction. There are four levels of abstraction in verilog. They are:
Behavioral or algorithmic level: This is the highest level of abstraction. A module can be implemented in terms of the design algorithm. The designer no need to have any knowledge of hardware implementation.Data flow level: In this level the module is designed by specifying the data flow. Designer must how data flows between various registers of the design.Gate level: The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design.Switch level: This is the lowest level of abstraction. The design is implemented using switches/transistors. Designer requires the knowledge of switch-level implementation details.
Gate-level modeling is virtually the lowest-level of abstraction, because t…

### Setup and Hold TIme

Every flip-flop has restrictive time regions around the active clock edge in which input should not change. We call them restrictive because any change in the input in this regions the output may be the expected one (*see below). It may be derived from either the old input, the new input, or even in between the two. Here we define, two very important terms in the digital clocking. Setup and Hold time.
The setup time is the interval before the clock where the data must be held stable.The hold time is the interval after the clock where the data must be held stable. Hold time can be negative, which means the data can change slightly before the clock edge and still be properly captured. Most of the current day flip-flops has zero or negative hold time.

In the above figure, the shaded region is the restricted region. The shaded region is divided into two parts by the dashed line. The left hand side part of shaded region is the setup time period and the right hand side part is the hold time…