VLSI Interview Questions

VLSI Interview Questions - 4

1. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?
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2. What are static and dynamic power dissipation w.r.t to CMOS gate?
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3. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) considering Channel Length Modulation.
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4. Which is fastest among the following technologies: CMOS, BiCMOS, TTL, ECL?
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5. What is a transmission gate, and what is its typical use in VLSI?
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6. Draw the cross section of nMOS or pMOS.
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7. What should be done to the size of a pMOS transistor inorder to increase its threshold voltage?
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8. Explain the various MOSFET Capacitances and their significance.
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9. On what factors does the resistance of metal depend on?
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10. Draw the layout a CMOS NAND gate.
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Digital Design Interview Questions - All in 1

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)? Answer 2. Implement an 2-input AND gate using a 2x1 mux. Answer 3. What is a multiplexer? Answer A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output. 4. What is a ring counter? Answer A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on. 5. Compare and Contrast Synchronous and Asynchronous reset. Answer Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for sma

XMR: Cross Module Reference

Cross Module Reference Cross Module Reference abbreviated as XMR is a very useful concept in Verilog HDL (as well as system Verilog). However it seems to be less known among many users of Verilog. XMR is a mechanism built into Verilog to globally reference (i.e., across the modules) to any nets, tasks, functions etc. Using XMR, one can refer to any object of a module in any other module, irrespective of whether they are present below or above its hierarchy. Hence, a XMR can be a: Downward reference OR Upward reference Consider the following hierarchy: Module A Net x Instance P of Module B Net x Instance M of Module D Net x Instance Q of Module C Net x Instance N of Module E Net x Instance R of Module B Net x Instance M of Module D Net x In test bench: Instance top of Module A In the above scenario, there is a

Synchronous Reset vs. Asynchronous Reset

Why Reset? A Reset is required to initialize a hardware design for system operation and to force an ASIC into a known state for simulation. A reset simply changes the state of the device/design/ASIC to a user/designer defined state. There are two types of reset, what are they? As you can guess them, they are Synchronous reset and Asynchronous reset. Synchronous Reset A synchronous reset signal will only affect or reset the state of the flip-flop on the active edge of the clock. The reset signal is applied as is any other input to the state machine. Advantages: The advantage to this type of topology is that the reset presented to all functional flip-flops is fully synchronous to the clock and will always meet the reset recovery time. Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be

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