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Modules

A module is the basic building block in Verilog HDL. In general many elements are grouped to form a module, to provide a common functionality, which can be used at many places in the design. Port interface (using input and output ports) helps in providing the necessary functionality to the higher-level blocks. Thus any design modifications at lower level can be easily implemented without affecting the entire design code. The structure of a module is show in the figure below.
Keyword module is used to begin a module and it ends with the keyword endmodule. The syntax is as follows:
module module_name
---
// internals
---
endmodule

Example: D Flip-flop implementation (Try to understand the module structure, ignore unknown constraints/statements).

module D_FlipFlop(q, d, clk, reset);

// Port declarations
output q;
reg q;
input d, clk, reset;

// Internal statements - Logic
always @(posedge reset or poseedge clk)
if (reset)
q < = 1'b0;
else
q < = d;

// endmodule statement
endmodule

Note:

  • Multiple modules can be defined in a single design file with any order.
  • See that the endmodule statement should not written as endmodule; (no ; is used).
  • All components except module, module name, and endmodule are optional.
  • The 5 internal components can come in any order.



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