Skip to main content

Modules

A module is the basic building block in Verilog HDL. In general many elements are grouped to form a module, to provide a common functionality, which can be used at many places in the design. Port interface (using input and output ports) helps in providing the necessary functionality to the higher-level blocks. Thus any design modifications at lower level can be easily implemented without affecting the entire design code. The structure of a module is show in the figure below.
Keyword module is used to begin a module and it ends with the keyword endmodule. The syntax is as follows:
module module_name
---
// internals
---
endmodule

Example: D Flip-flop implementation (Try to understand the module structure, ignore unknown constraints/statements).

module D_FlipFlop(q, d, clk, reset);

// Port declarations
output q;
reg q;
input d, clk, reset;

// Internal statements - Logic
always @(posedge reset or poseedge clk)
if (reset)
q < = 1'b0;
else
q < = d;

// endmodule statement
endmodule

Note:
  • Multiple modules can be defined in a single design file with any order.
  • See that the endmodule statement should not written as endmodule; (no ; is used).
  • All components except module, module name, and endmodule are optional.
  • The 5 internal components can come in any order.



<< Previous Home  Next >>   

 
Labels:

Comments

Post a Comment

Popular posts from this blog

Digital Design Interview Questions - All in 1

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)? Answer 2. Implement an 2-input AND gate using a 2x1 mux. Answer 3. What is a multiplexer? Answer A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output. 4. What is a ring counter? Answer A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on. 5. Compare and Contrast Synchronous and Asynchronous reset. Answer Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for sma...
223 comments
Read more

XMR: Cross Module Reference

Cross Module Reference   Cross Module Reference abbreviated as XMR is a very useful concept in Verilog HDL (as well as system Verilog). However it seems to be less known among many users of Verilog. XMR is a mechanism built into Verilog to globally reference (i.e., across the modules) to any nets, tasks, functions etc. Using XMR, one can refer to any object of a module in any other module, irrespective of whether they are present below or above its hierarchy. Hence, a XMR can be a:   Downward reference OR Upward reference   Consider the following hierarchy:     Module A   Net x   Instance P of Module B     Net x   Instance M of Module D   Net x   Instance Q of Module C   Net x   Instance N of Module E    Net x   Instance R of Module B   Net x   Instance M of Module D   Net x ...
5 comments
Read more

One-hot Encoding

Designing a FSM is the most common and challenging task for every digital logic designer. One of the key factors for optimizing a FSM design is the choice of state coding, which influences the complexity of the logic functions, the hardware costs of the circuits, timing issues, power usage, etc. There are several options like binary encoding, gray encoding, one-hot encoding, etc. The choice of the designer depends on the factors like technology, design specifications, etc. One-hot encoding In one-hot encoding only one bit of the state vector is asserted for any given state. All other state bits are zero. Thus if there are n states then n state flip-flops are required. As only one bit remains logic high and rest are logic low, it is called as One-hot encoding. Example : If there is a FSM, which has 5 states. Then 5 flip-flops are required to implement the FSM using one-hot encoding. The states will have the following values: S0 - 10000 S1 - 01000 S2 - 00100 S3 - 00010 S4 - 00001 Adv...
Post a Comment
Read more