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Verilog Interview Questions - 1

Questions are related to comparison (What is the difference betweem ...).

1. What is the difference between a function and a task?
Answer

2. What is the difference between $display and $monitor?
Answer

3. What is the difference between wire and reg?
Answer

4. What is the difference between blocking and non-blocking assignments?
Answer

5. What is the difference between casex, casez and case statements?
Answer

6. What is the difference between transport delay and inertial delay?
Answer

7. What is the difference between unary and logical operators?
Answer

8. What is the difference between compiled, interpreted, event based and cycle based simulators?
Answer

9. What is the difference between ( = = , ! = ) and ( = = = , ! = = )?
Answer

10. What are the difference between Verilog and VHDL?
Answer

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Anonymous said…
Give a link to go to the next page at the end of the questions. So everyone will aware of that few more pages of interview questions left.

place a "next page" link at end of the questions above comments.

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