Verilog Interview Questions - 1

Questions are related to comparison (What is the difference betweem ...).

1. What is the difference between a function and a task?
Answer


2. What is the difference between $display and $monitor?
Answer

3. What is the difference between wire and reg?
Answer

4. What is the difference between blocking and non-blocking assignments?
Answer

5. What is the difference between casex, casez and case statements?
Answer

6. What is the difference between transport delay and inertial delay?
Answer

7. What is the difference between unary and logical operators?
Answer

8. What is the difference between compiled, interpreted, event based and cycle based simulators?
Answer

9. What is the difference between ( = = , ! = ) and ( = = = , ! = = )?
Answer

10. What are the difference between Verilog and VHDL?
Answer

12 Comments:

bologna03 said...

Hi

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Let me introduce other material that may be good for our community.

Source: Sample interview questions

Best regards
Henry

Interview Questions said...

Thanks for sharing valuable interview questions.

Interview Questions

gp said...

thanks a lot

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Anonymous said...

Cycle based Simulator :Cycle simulation is a technique (i.e. an algorithm) for digital circuit simulation. It does not simulate detailed circuit timing, but instead computes the steady state response of a circuit at each clock cycle. The user cannot see the glitch behavior of signals between clock cycles. Instead the user observes circuit signals once per clock cycle. Cycle based simulators work only with synchronous designs.
Event based Simulator: Simulation based on events in logic means that whenever there is change in a input event, the output is evaluated. This makes the simulation very slow compared to Cycle based simulators. Verilog-XL is an event based simulator.

Compiled Simulator : This kind of simulator converts the whole Verilog code into machine dependent code and then runs the simulation. Example : VCS generates the binary file, which can be run from the command prompt. Compiled simulators are very fast.
Interpreted Simulator : This kind of simulator executes line by line, thus is very slow compared to a compiled simulator. Verilog-XL is one such simulator.

Anonymous said...

Question 7:
7. What is the difference between unary and logical operators?
The Answer was:


Unary operators have only one operand, where as logical operators are of two operands.

I guess that both - the question and the answer are not exactly correct.
a = !b - unary logical operator
Did you mean a difference between bitwise and logical, say "&" and "&&"

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Himanshu Chauhan said...

Thanx keep on posting such a valuable material

p.krishna said...

thank you

p.krishna said...

thank you

shashi uppuganti said...

Very useful data...keep on postng.

Anonymous said...

The links posted above for sample questions and interview questions dont work. Please fix them. Cheers !

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