- 0 - represents a logic zero, or a false condition.
- 1 - represents a logic one, or a true condition.
- x - represents an unknown logic value.
- z - represents a high-impedance state.
Nets are used to make connections between hardware elements. Nets simply reflect the value at one end(head) to the other end(tail). It means the value they carry is continuously driven by the output of a hardware element to which they are connected to. Nets are generally declared using the keyword wire. The default value of net (wire) is z. If a net has no driver, then its value is z.
Registers are data storage elements. They hold the value until they are replaced by some other value. Register doesn't need a driver, they can be changed at anytime in a simulation. Registers are generally declared with the keyword reg. Its default value is x. Register data types should not be confused with hardware registers, these are simply variables.
Integer is a register data type of 32 bits. The only difference of declaring it as integer is that, it becomes a signed value. When you declare it as a 32 bit register (array) it is an unsigned value. It is declared using the keyword integer.
Real number can be declared using the keyword real. They can be assigned values as follows:
r_1 = 1.234; // Decimal notation.
r_1 = 3e4; // Scientific notation.
Parameters are the constants that can be declared using the keyword parameter. Parameters are in general used for customization of a design. Parameters are declared as follows:
parameter p_1 = 123; // p_1 is a constant with value 123.
Keyword defparam can be used to change a parameter value at module instantiation. Keyword localparam is usedd to declare local parameters, this is used when their value should not be changed.
Vectors can be a net or reg data types. They are declared as [high:low] or [low:high], but the left number is always the MSB of the vector.
wire [7:0] v_1; // v_1 is the MSB.
reg [0:15] v_2; // v_2 is the MSB.
In the above examples: If it is written as v_1[5:2], it is the part of the entire vector which contains 4 bits in order: v_1, v_1, v_1, v_1. Similarly v_2[0:7], means the first half part of the vecotr v_2.
Vector parts can also be specified in a different way:
vector_name[start_bit+:width] : part-select increments from start_bit. In above example: v_2[0:7] is same as v_2[0+:8]. vector_name[start_bit-:width] : part-select decrements from start_bit. In above example: v_1[5:2] is same as v_1[5-:4].
Arrays of reg, integer, real, time, and vectors are allowed. Arrays are declared as follows:
wire [0:3] a_4[7:0]; // Array of vector
integer a_5[0:3][6:0]; // Double dimensional array
Strings are register data types. For storing a character, we need a 8-bit register data type. So if you want to create string variable of length n. The string should be declared as register data type of length n*8.
reg [8*8-1:0] string_1; // string_1 is a string of length 8.
Time Data Type
Time data type is declared using the keyword time. These are generally used to store simulation time. In general it is 64-bit long.
t_1 = $time; // assigns current simulation time to t_1.
There are some other data types, but are considered to be advanced data types, hence they are not discussed here.
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