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The Verilog HDL is defined in terms of a discrete event execution model. A design consists of connected processes. Processes are objects that can be evaluated, that may have state, and that can respond to changes on their inputs to produce outputs. Processes include primitives, modules, initial and always procedural blocks, continuous assignments, asynchronous tasks, and procedural assignment statements.

The following definitions helps in better understanding of scheduling and execution of events:
  • Update event: Every change in value of a net or variable in the circuit being simulated, as well as the named event, is considered as an update event.
  • Evaluation event: Processes are sensitive to update events. When an update event is executed, all the processes that are sensitive to that event are evaluated in an arbitrary order. The evaluation of a process is also an event, known as an evaluation event.
  • Simulation time: It is used to refer to the time value maintained by the simulator to model the actual time it would take for the circuit being simulated.
Events can occur at different times. In order to keep track of the events and to make sure they are processed in the correct order, the events are kept on an event queue, ordered by simulation time. Putting an event on the queue is called scheduling an event.

Scheduling events:

The Verilog event queue is logically segmented into five different regions. Each event will be added to one of the five regions in the queue but are only removed from the active region.
  1. Active events: Events that occur at the current simulation time and can be processed in any order.
  2. Inactive events: Events that occur at the current simulation time, but that shall be processed after all the active events are processed.
  3. Nonblocking assign update events: Events that have been evaluated during some previous simulation time, but that shall be assigned at this simulation time after all the active and inactive events are processed.
  4. Monitor events: Events that shall be processed after all the active, inactive, and nonblocking assign update events are processed.
  5. Future events: Events that occur at some future simulation time. Future events are divided into future inactive events, and future nonblocking assignment update events.
The processing of all the active events is called a simulation cycle.


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Gate-Level Modeling

>> Introduction
>> Gate Primitives
>> Delays
>> Examples


In Verilog HDL a module can be defined using various levels of abstraction. There are four levels of abstraction in verilog. They are:
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