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The Verilog HDL is defined in terms of a discrete event execution model. A design consists of connected processes. Processes are objects that can be evaluated, that may have state, and that can respond to changes on their inputs to produce outputs. Processes include primitives, modules, initial and always procedural blocks, continuous assignments, asynchronous tasks, and procedural assignment statements.

The following definitions helps in better understanding of scheduling and execution of events:
  • Update event: Every change in value of a net or variable in the circuit being simulated, as well as the named event, is considered as an update event.
  • Evaluation event: Processes are sensitive to update events. When an update event is executed, all the processes that are sensitive to that event are evaluated in an arbitrary order. The evaluation of a process is also an event, known as an evaluation event.
  • Simulation time: It is used to refer to the time value maintained by the simulator to model the actual time it would take for the circuit being simulated.
Events can occur at different times. In order to keep track of the events and to make sure they are processed in the correct order, the events are kept on an event queue, ordered by simulation time. Putting an event on the queue is called scheduling an event.

Scheduling events:

The Verilog event queue is logically segmented into five different regions. Each event will be added to one of the five regions in the queue but are only removed from the active region.
  1. Active events: Events that occur at the current simulation time and can be processed in any order.
  2. Inactive events: Events that occur at the current simulation time, but that shall be processed after all the active events are processed.
  3. Nonblocking assign update events: Events that have been evaluated during some previous simulation time, but that shall be assigned at this simulation time after all the active and inactive events are processed.
  4. Monitor events: Events that shall be processed after all the active, inactive, and nonblocking assign update events are processed.
  5. Future events: Events that occur at some future simulation time. Future events are divided into future inactive events, and future nonblocking assignment update events.
The processing of all the active events is called a simulation cycle.


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2. Implement an 2-input AND gate using a 2x1 mux.

3. What is a multiplexer?

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4. What is a ring counter?

A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on.

5. Compare and Contrast Synchronous and Asynchronous reset.

Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for small reset gl…

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>> Introduction
>> Gate Primitives
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In Verilog HDL a module can be defined using various levels of abstraction. There are four levels of abstraction in verilog. They are:
Behavioral or algorithmic level: This is the highest level of abstraction. A module can be implemented in terms of the design algorithm. The designer no need to have any knowledge of hardware implementation.Data flow level: In this level the module is designed by specifying the data flow. Designer must how data flows between various registers of the design.Gate level: The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design.Switch level: This is the lowest level of abstraction. The design is implemented using switches/transistors. Designer requires the knowledge of switch-level implementation details.
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Why Reset?

A Reset is required to initialize a hardware design for system operation and to force an ASIC into a known state for simulation.

A reset simply changes the state of the device/design/ASIC to a user/designer defined state. There are two types of reset, what are they? As you can guess them, they are Synchronous reset and Asynchronous reset.

Synchronous Reset

A synchronous reset signal will only affect or reset the state of the flip-flop on the active edge of the clock. The reset signal is applied as is any other input to the state machine.

The advantage to this type of topology is that the reset presented to all functional flip-flops is fully synchronous to the clock and will always meet the reset recovery time.Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant…