Verilog Interview Questions - 2

1. Given the following Verilog code, what value of "a" is displayed?
always @(clk)
begin
a = 0;
a < = 1;
$display(a);
end
Answer

Verilog used four-level deep queue for the current simulation time:
1. Active events (blocking statements).
2. Inactive events (#0 delays, etc).
3. Non-blocking assign updates (non-blocking statements).
4. Monitor Events ($display, $monitor).

So $display(a); displays 0.

2. What is the difference between a = #10 b; and #10 a = b; ?
Answer

In a = #10 b; current value of "b" will be assigned to "a" after 10 units of time (like transport delay). In #10 a = b; the simulator will execute a = b; after 10 units of time (like inertial delay).

3. Let "a" be a 3 bit reg value.
initial
begin
a < = 3'b101;
a = #5 3'b000;
a < = #10 3'b111;
a < = #30 3'b011;
a = #20 3'b010;
a < = #5 3'b110;
end
What will be the value of "a" at time 0,5,10,... units till 40 units of time?
Answer

0 - 101
5 - 000
10 - 000
15 - 111
20 - 111
25 - 010
30 - 110
35 - 011
40 - 011
(This helps in understanding the concepts of blocking and non-blocking statements).

4. Write a verilog code to swap contents of two registers with and without using a temporary register.
Answer

With a temporary register:
always @ (posedge clock)
begin
temp_reg=b;
b=a;
a=temp_reg;
end

Without using a temporary register:
always @ (posedge clock)
begin
a < = b;
b < = a;
end

5. What is the difference between:
c = check ? a : b; and
if(check) c = a;
else c = b;
Answer

The ?: merges answers if the condition is 'x', so if check = 1'bx, a=2'b10, and c=2'b11, then c = 2'b1x. Where as if else treats x or z as false case, so always c = b.

6. What does `timescale 1 ns/ 1 ps’ signify in a verilog code?
Answer

It means the unit of time is 1ns and the precision/accuracy will be up to 1ps.

7. what is the use of defparam?
Answer

Parameter values can be changed in any module instance in the design with the keyword defparam.

8. What is a sensitivity list?
Answer

All input signals that cause a re-computation of out to occur must go into the always @(...), which as a group are called as sensitivity list.

9. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity list? If yes, why? If not, why?
Answer

Yes, in a combinational circuit, if an input at one of the input terminals changes then the gate re-computes its output. Hence to make it happen in our design, it is must to put all input signals in sensitivity list.

10. How to generate sine wave using verilog coding style?
Answer

The easiest and efficient way to generate sine wave is using CORDIC algorithm.