Verilog Interview Questions - 2

1. Given the following Verilog code, what value of "a" is displayed?
always @(clk)
begin
a = 0;
a < = 1;
$display(a);
end
Answer


2. What is the difference between a = #10 b; and #10 a = b; ?
Answer

3. Let "a" be a 3 bit reg value.
initial
begin
a < = 3'b101;
a = #5 3'b000;
a < = #10 3'b111;
a < = #30 3'b011;
a = #20 3'b010;
a < = #5 3'b110;
end
What will be the value of "a" at time 0,5,10,... units till 40 units of time?
Answer

4. Write a verilog code to swap contents of two registers with and without using a temporary register.
Answer

5. What is the difference between:
c = check ? a : b; and
if(check) c = a;
else c = b;
Answer

6. What does `timescale 1 ns/ 1 ps’ signify in a verilog code?
Answer

7. what is the use of defparam?
Answer

8. What is a sensitivity list?
Answer

9. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity list? If yes, why? If not, why?
Answer

10. How to generate sine wave using verilog coding style?
Answer

9 Comments:

Anonymous said...

Hi,
good collection of Question, These are very small points but difficult to explain.

Anndy

Anonymous said...

.....the first answer is WRONG, it should be 1 as per your procedure.

Anonymous said...

sorry guys......the answer is right......never mind

Anonymous said...

9. Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch.

kushal parmar said...

Can anyone explain me the concept behind first question! am confused!

Anonymous said...

The $display occurs in the active events region. ( You have mentioned that it occurs in monitor events region, which is wrong)
$strobe and $moninor occur in monitor events.

So, the sequence of events is

1. a = 0;
2.display(a)
3. Evaluation of rhs of (a<=1), nothing to evaluate as 1 is constant
4.assign 1 to a

As, display occurs second, a=0 is the correct answer

Anonymous said...

For 3rd question.

Non-blocking statements are concurrent in a block

For ex: if we have

a <= #5 b'000;
a <= #10 b'001;

at time = 5, a = 000;
at time = 10, a = 001;

But, according to you, its
at time = 5, a = 000;
at time = 15, a = 001;
which I believe is wrong.

So, the answer according to me should be
0 - 101 ( a<=3'b101)
5- 000 (a = #5 3'b000)
5- 110 (a < = #5 3'b110) ( remember blocking statements are sequential, and if blocking and non-blocking statements occur at same time, then blocking assignment occur first, according to first question solution)
10 - 111 (a < = #10 3'b111)
25 - 010 (a = #20 3'b010)
30 011 (a < = #30 3'b011)

So, according to me sequence of events

a < = 3'b101 ( time = 0)
a = #5 3'b000;(time = 5)
a < = #5 3'b110;(time =5 but a time step later than blocking assignment)
a < = #10 3'b111 ( evaluated to 111 at t=0 but assigned at t=10)
a = #20 3'b010 (evaluated to 010 at t=0 but assigned at t=20)
a < = #30 3'b011 (evaluated to 011 at t=0 but assigned at t=30)

However, if we had a non-blocking statement like this,

#20;
a <= #5 3'b000;

Then , ofcourse it is considered as a=000 at t=20+5;
non-blocking assignments are concurrent, blocking are sequential.

Anonymous said...

In verilod execution takes place according to this..
blocking statements
zero delays statements
non blocking statements
Monitoring statements

so i relate this with question 1

Blocking statement will execute frst..

so ans will b a=0

Anonymous said...

Ans 4

with temp reg

always@(posedge clk)
begin
temp = b;
b=a;
a= temp;
end


without temp reg

always@(posedge clk)
begin
a<=b;
b<=a;
end
a=

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