1. Given the following Verilog code, what value of "a" is displayed?

always @(clk)

begin

a = 0;

a < = 1;

$display(a);

end

Answer

2. What is the difference between a = #10 b; and #10 a = b; ?

Answer

3. Let "a" be a 3 bit reg value.

initial

begin

a < = 3'b101;

a = #5 3'b000;

a < = #10 3'b111;

a < = #30 3'b011;

a = #20 3'b010;

a < = #5 3'b110;

end

What will be the value of "a" at time 0,5,10,... units till 40 units of time?

Answer

4. Write a verilog code to swap contents of two registers with and without using a temporary register.

Answer

5. What is the difference between:

c = check ? a : b; and

if(check) c = a;

else c = b;

Answer

6. What does `timescale 1 ns/ 1 ps’ signify in a verilog code?

Answer

7. what is the use of defparam?

Answer

8. What is a sensitivity list?

Answer

9. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity list? If yes, why? If not, why?

Answer

10. How to generate sine wave using verilog coding style?

Answer

always @(clk)

begin

a = 0;

a < = 1;

$display(a);

end

Answer

2. What is the difference between a = #10 b; and #10 a = b; ?

Answer

3. Let "a" be a 3 bit reg value.

initial

begin

a < = 3'b101;

a = #5 3'b000;

a < = #10 3'b111;

a < = #30 3'b011;

a = #20 3'b010;

a < = #5 3'b110;

end

What will be the value of "a" at time 0,5,10,... units till 40 units of time?

Answer

4. Write a verilog code to swap contents of two registers with and without using a temporary register.

Answer

5. What is the difference between:

c = check ? a : b; and

if(check) c = a;

else c = b;

Answer

6. What does `timescale 1 ns/ 1 ps’ signify in a verilog code?

Answer

7. what is the use of defparam?

Answer

8. What is a sensitivity list?

Answer

9. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity list? If yes, why? If not, why?

Answer

10. How to generate sine wave using verilog coding style?

Answer

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