Skip to main content

Ports

Modules communicate with external world using ports. They provide interface to the modules. A module definition contains list of ports. All ports in the list of ports must be declared in the module, ports can be one the following types:
  • Input port, declared using keyword input.
  • Output port, declared using keyword output.
  • Bidirectional port, declared using keyword inout.
All the ports declared are considered to be as wire by default. If a port is intended to be a wire, it is sufficient to declare it as output, input, or inout. If output port holds its value it should be declared as reg type. Ports of type input and inout cannot be declared as reg because reg variables hold values and input ports should not hold values but simply reflect the changes in the external signals they are connected to.

Port Connection Rules
  • Inputs: Always of type net(wire). Externally, they can be connected to reg or net type variable.
  • Outputs: Can be of reg or net type. Externally, they must be connected to a net type variable.
  • Bidirectional ports (inout): Always of type net. Externally, they must be connected to a net type variable.
Note:
  • It is possible to connect internal and external ports of different size. In general you will receive a warning message for width mismatch.
  • There can be unconnected ports in module instances.
Ports can declared in a module in C-language style:

module module_1( input a, input b, output c);
--
// Internals
--
endmodule

If there is an instance of above module, in some other module. Port connections can be made in two types.

Connection by Ordered List:
module_1 instance_name_1 ( A, B, C);
Connecting ports by name:
module_1 instance_name_2 (.a(A), .c(C), .b(B));

In connecting port by name, order is ignored.


<< Previous Home  Next >>   

 

Comments

Popular posts from this blog

Digital Design Interview Questions - All in 1

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)?
Answer



2. Implement an 2-input AND gate using a 2x1 mux.
Answer



3. What is a multiplexer?
Answer

A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output.

4. What is a ring counter?
Answer

A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on.

5. Compare and Contrast Synchronous and Asynchronous reset.
Answer

Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for small reset gl…

Setup and Hold TIme

Every flip-flop has restrictive time regions around the active clock edge in which input should not change. We call them restrictive because any change in the input in this regions the output may be the expected one (*see below). It may be derived from either the old input, the new input, or even in between the two. Here we define, two very important terms in the digital clocking. Setup and Hold time.
The setup time is the interval before the clock where the data must be held stable.The hold time is the interval after the clock where the data must be held stable. Hold time can be negative, which means the data can change slightly before the clock edge and still be properly captured. Most of the current day flip-flops has zero or negative hold time.


In the above figure, the shaded region is the restricted region. The shaded region is divided into two parts by the dashed line. The left hand side part of shaded region is the setup time period and the right hand side part is the hold time…

Gate-Level Modeling

>> Introduction
>> Gate Primitives
>> Delays
>> Examples


Introduction

In Verilog HDL a module can be defined using various levels of abstraction. There are four levels of abstraction in verilog. They are:
Behavioral or algorithmic level: This is the highest level of abstraction. A module can be implemented in terms of the design algorithm. The designer no need to have any knowledge of hardware implementation.Data flow level: In this level the module is designed by specifying the data flow. Designer must how data flows between various registers of the design.Gate level: The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design.Switch level: This is the lowest level of abstraction. The design is implemented using switches/transistors. Designer requires the knowledge of switch-level implementation details.
Gate-level modeling is virtually the lowest-level of abstraction, because t…