1. What are set up time and hold time constraints?

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2. Give a circuit to divide frequency of clock cycle by two.

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3. Design a divide-by-3 sequential circuit with 50% duty circle.

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4. Explain different types of adder circuits.

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5. Give two ways of converting a two input NAND gate to an inverter.

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6. Draw a Transmission Gate-based D-Latch.

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7. Design a FSM which detects the sequence 10101 from a serial line without overlapping.

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8. Design a FSM which detects the sequence 10101 from a serial line with overlapping.

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9. Give the design of 8x1 multiplexer using 2x1 multiplexers.

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10. Design a counter which counts from 1 to 10 ( Resets to 1, after 10 ).

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## 2 Comments:

The Transmission-Gate input is connected to the D_LATCH data input (D), the control input to the Transmission-Gate is connected to the D_LATCH enable input (EN) and the Transmission-Gate output is the D_LATCH output (Q)

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