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Introduction to SystemVerilog

SystemVerilog

SystemVerilog is a combined hardware description language (HDL) and hardware verification language (HVL) based on extensions to Verilog HDL.

SystemVerilog as a RTL design language is an extension of Verilog HDL containing all features of Verilog. As a verification language SystemVerilog uses object-oriented programming (OOP) techniques similar to that of C++, Java etc. Clearly, the main advantage of SystemVerilog is the unification of HDL and HVL, that provides a single platform for RTL design and verification.

As a HDL SystemVerilog supports C/C++ like features including typedef, struct, union, enum, etc. These new features can be used for faster and efficient implementation of HDL, increasing the productivity of RTL design process. However, SystemVerilog’s strongest suite comes as a HVL.  It provides a complete verification environment supporting constraint random generation, assertion based verification and coverage driven verification.

Some of the SystemVerilog featu…

XMR: Cross Module Reference

Cross Module Reference

Cross Module Reference abbreviated as XMR is a very useful concept in Verilog HDL (as well as system Verilog). However it seems to be less known among many users of Verilog.
XMR is a mechanism built into Verilog to globally reference (i.e., across the modules) to any nets, tasks, functions etc. Using XMR, one can refer to any object of a module in any other module, irrespective of whether they are present below or above its hierarchy. Hence, a XMR can be a: Downward reference ORUpward reference
Consider the following hierarchy: Module ANet xInstance P of Module BNet xInstance M of Module DNet xInstance Q of Module CNet xInstance N of Module E  Net xInstance R of Module BNet xInstance M of Module DNet x
In test bench: Instance top of Module A
In the above scenario, there is a net named x in all modules. Using XMR each x can be globally referenced anywhere within the test bench hierarchy as follows. top.xtop.P.xt…

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