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Introduction to SystemVerilog

SystemVerilog

SystemVerilog is a combined hardware description language (HDL) and hardware verification language (HVL) based on extensions to Verilog HDL.

SystemVerilog as a RTL design language is an extension of Verilog HDL containing all features of Verilog. As a verification language SystemVerilog uses object-oriented programming (OOP) techniques similar to that of C++, Java etc. Clearly, the main advantage of SystemVerilog is the unification of HDL and HVL, that provides a single platform for RTL design and verification.

As a HDL SystemVerilog supports C/C++ like features including typedef, struct, union, enum, etc. These new features can be used for faster and efficient implementation of HDL, increasing the productivity of RTL design process. However, SystemVerilog’s strongest suite comes as a HVL.  It provides a complete verification environment supporting constraint random generation, assertion based verification and coverage driven verification.

Some of the SystemVerilog features  include:
  • C type data types int, shortint, etc.
  • User defined data types using typedef, struct, union, enum
  • Dynamic data types
  • Classes for object oriented programming
  • More operators (like ++, –)
  • Assertions and coverage.
The subsequent chapters in this SystemVerilog tutorial will focus on concepts that are new to SystemVerilog, compared to Verilog. So, it would beneficial to refresh your knowledge of Verilog. Tutorial on Verilog is already available on Only-VLSI.

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