Skip to main content

Basics: Lexical Tokens

>> Operators
>> Comments
>> Whitespace
>> Strings
>> Identifiers
>> Keywords
>> Number Specification


Operators

There are three types of operators: unary, binary, and ternary, which have one, two, and three operands respectively.

Unary : Single operand, which precede the operand.
Ex: x = ~y
~ is a unary operator
y is the operand

binary : Comes between two operands.
Ex: x = y || z
|| is a binary operator
y and z are the operands

ternary : Ternary operators have two separate operators that separate three operands.
Ex: p = x ? y : z
? : is a ternary operator
x, y, and z are the operands

List of operators is given here.

Comments

Verilog HDL also have two types of commenting, similar to that of C programming language. // is used for single line commenting and '/*' and '*/' are used for commenting multiple lines which start with /* and end with */.
EX: // single line comment
/* Multiple line
commenting */
/* This is a // LEGAL comment */
/* This is an /* ILLEGAL */ comment */

Whitespace
  • - \b - backspace
  • - \t - tab space
  • - \n - new line
In verilog Whitespace is ignored except when it separates tokens. Whitespace is not ignored in strings. Whitesapces are generally used in writing test benches.

Strings

A string in verilog is same as that of C programming language. It is a sequence of characters enclosed in double quotes. String are treated as sequence of one byte ASCII values, hence they can be of one line only, they cannot be of multiple lines.
Ex: " This is a string "
" This is not treated as
string in verilog HDL "

Identifiers

Identifiers are user-defined words for variables, function names, module names, block names and instance names.Identifiers begin with a letter or underscore and can include any number of letters, digits and underscores. It is not legal to start identifiers with number or the dollar($) symbol in Verilog HDL. Identifiers in Verilog are case-sensitive.

Keywords

Keywords are special words reserved to define the language constructs. In verilog all keywords are in lowercase only. A list of all keywords in Verilog is given below:

always
and
assign
attribute
begin
buf
bufif0
bufif1
case
casex
casez
cmos
deassign
default
defparam
disable
edge
else
end
endattribute
endcase
endfunction
endmodule
endprimitive
endspecify
endtable
endtask		event
for
force
forever
fork
function
highz0
highz1
if
ifnone
initial
inout
input
integer
join
medium
module
large
macromodule
nand
negedge
nmos
nor
not
notif0
notif1
or		output
parameter
pmos
posedge
primitive
pull0
pull1
pulldown
pullup
rcmos
real
realtime
reg
release
repeat
rnmos
rpmos
rtran
rtranif0
rtranif1
scalared
signed
small
specify
specparam
strength
strong0		strong1
supply0
supply1
table
task
time
tran
tranif0
tranif1
tri
tri0
tri1
triand
trior
trireg
unsigned
vectored
wait
wand
weak0
weak1
while
wire
wor
xnor
xor


Verilog keywords also includes compiler directives, system tasks, and functions. Most of the keywords will be explained in the later sections.

Number Specification

Sized Number Specification

Representation: [size]'[base][number]
  • [size] is written only in decimal and specifies the number of bits.
  • [base] could be 'd' or 'D' for decimal, 'h' or 'H' for hexadecimal, 'b' or 'B' for binary, and 'o' or 'O' for octal.
  • [number] The number is specified as consecutive digits. Uppercase letters are legal for number specification (in case of hexadecimal numbers).
Ex: 4'b1111 : 4-bit binary number
16'h1A2F : 16-bit hexadecimal number
32'd1 : 32-bit decimal number
8'o3 : 8-bit octal number

Unsized Number Specification

By default numbers that are specified without a [base] specification are decimal numbers. Numbers that are written without a [size] specification have a default number of bits that is simulator and/or machine specific (generally 32).

Ex: 123 : This is a decimal number
'hc3 : This is a hexadecimal number
Number of bits depends on simulator/machine, generally 32.

x or z values

x - Unknown value.
z - High impedance value
An x or z sets four bits for a number in the hexadecimal base, three bits for a number in the octal base, and one bit for a number in the binary base.

Note: If the most significant bit of a number is 0, x, or z, the number is automatically extended to fill the most significant bits, respectively, with 0, x, or z. This makes it easy to assign x or z to whole vector. If the most significant digit is 1, then it is also zero extended.

Negative Numbers

Representation: -[size]'[base][number]

Ex: -8'd9 : 8-bit negative number stored as 2's complement of 8
-8'sd3 : Used for performing signed integer math
4'd-2 : Illegal

Underscore(_) and question(?) mark

An underscore, "_" is allowed to use anywhere in a number except in the beginning. It is used only to improve readability of numbers and are ignored by Verilog. A question mark "?" is the alternative for z w.r.t. numbers
Ex: 8'b1100_1101 : Underscore improves readability
4'b1??1 : same as 4'b1zz1


<< Previous Home  Next >>   

 
Labels:

Comments

Post a Comment

Popular posts from this blog

Digital Design Interview Questions - All in 1

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)? Answer 2. Implement an 2-input AND gate using a 2x1 mux. Answer 3. What is a multiplexer? Answer A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output. 4. What is a ring counter? Answer A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on. 5. Compare and Contrast Synchronous and Asynchronous reset. Answer Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for sma...
223 comments
Read more

XMR: Cross Module Reference

Cross Module Reference   Cross Module Reference abbreviated as XMR is a very useful concept in Verilog HDL (as well as system Verilog). However it seems to be less known among many users of Verilog. XMR is a mechanism built into Verilog to globally reference (i.e., across the modules) to any nets, tasks, functions etc. Using XMR, one can refer to any object of a module in any other module, irrespective of whether they are present below or above its hierarchy. Hence, a XMR can be a:   Downward reference OR Upward reference   Consider the following hierarchy:     Module A   Net x   Instance P of Module B     Net x   Instance M of Module D   Net x   Instance Q of Module C   Net x   Instance N of Module E    Net x   Instance R of Module B   Net x   Instance M of Module D   Net x ...
5 comments
Read more

One-hot Encoding

Designing a FSM is the most common and challenging task for every digital logic designer. One of the key factors for optimizing a FSM design is the choice of state coding, which influences the complexity of the logic functions, the hardware costs of the circuits, timing issues, power usage, etc. There are several options like binary encoding, gray encoding, one-hot encoding, etc. The choice of the designer depends on the factors like technology, design specifications, etc. One-hot encoding In one-hot encoding only one bit of the state vector is asserted for any given state. All other state bits are zero. Thus if there are n states then n state flip-flops are required. As only one bit remains logic high and rest are logic low, it is called as One-hot encoding. Example : If there is a FSM, which has 5 states. Then 5 flip-flops are required to implement the FSM using one-hot encoding. The states will have the following values: S0 - 10000 S1 - 01000 S2 - 00100 S3 - 00010 S4 - 00001 Adv...
Post a Comment
Read more