Skip to main content


Showing posts from 2009

Synchronous Reset vs. Asynchronous Reset

Why Reset?

A Reset is required to initialize a hardware design for system operation and to force an ASIC into a known state for simulation.

A reset simply changes the state of the device/design/ASIC to a user/designer defined state. There are two types of reset, what are they? As you can guess them, they are Synchronous reset and Asynchronous reset.

Synchronous Reset

A synchronous reset signal will only affect or reset the state of the flip-flop on the active edge of the clock. The reset signal is applied as is any other input to the state machine.

The advantage to this type of topology is that the reset presented to all functional flip-flops is fully synchronous to the clock and will always meet the reset recovery time.Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant…

VLSI Interview Questions with Answers - 1

1. Why does the present VLSI circuits use MOSFETs instead of BJTs?

Compared to BJTs, MOSFETs can be made very small as they occupy very small silicon area on IC chip and are relatively simple in terms of manufacturing. Moreover digital and memory ICs can be implemented with circuits that use only MOSFETs i.e. no resistors, diodes, etc.

2. What are the various regions of operation of MOSFET? How are those regions used?

MOSFET has three regions of operation: the cut-off region, the triode region, and the saturation region.
The cut-off region and the triode region are used to operate as switch. The saturation region is used to operate as amplifier.

3. What is threshold voltage?

The value of voltage between Gate and Source i.e. VGS at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called threshold voltage (Vt is positive for NMOS and negative for PMOS).

4. What does it mean "the channel is pinched off"?

Type-3: Give Verilog/VHDL code ...

Most Common Interview Questions: Type-3: Give Verilog/VHDL code ...

The prime intention of the interviewer in asking this question is to see the hands-on experience you have. If you have mentioned that you are familiar with Verilog/VHDL in your resume and attending an ASIC engineer post, then you can expect this question. This question usually comes after asking Type-1 and/or Type-2 questions (explained in previous posts). No interviewer starts with this type of question.

The common strategy followed is: initially you will be asked "Type-1: Design a ..." and then as an extension you will be asked to code it in Verilog or VHDL. Further, the interviewer may specifically ask you, to code for synthesis.

This question is asked to test your ability to code. Don't ever write a psuedo code or a code with syntax error(s).Prepare for this question by coding some basic programs like flip-flops, counters, small FSMs etc. Make sure that you touch most of the commonly used Verilog/VH…

Type-2: Tell us about a design/project you worked on

Most Common Interview Questions: Type-2: Tell us about a design/project you worked on

Prepare for answering this question in any interview you attend, its kind of inevitable. Usually our resumes will be flooded with some projects. So an interviewer, instead of asking about one of those projects, he simply hits the ball into your court by asking this question. In general, interviewers ask to talk about your best work, it could be a design you made out of your interest or a project or part of a coursework. Irrespective of whether interviewer uses the word best its implied that you are going to talk about your best work! Now the ball is in your court you have to give a smart reply using your skills.

How to answer this question?

Remember that the time you have to answer this is limited. So instead of explaining every aspect of your design in detail, give glimpses of your design. Start taking about the best or challenging part of your design. This is best way of extracting some questions fro…

Type-1: Design a ...

Most Common Interview Questions: Type-1: Design a ...

This is the most common question one will face in his/her interview, probably the first question which starts testing your knowledge. (I mean this comes after introduction and "Tell us about yourself"). This is a lethal weapon used by the interviewer to test one's abilities: both weak and strong points. The concepts required for solving the problem are generally related to the type of job you are being tested for.

The most popular strategy used by the interview in this question is gradual increase in the complexity of the question. It goes like this ... Interviewer states the specifications of the design. You can present as simple/straight forward/redundant answer as possible. The next question could be redesign using only NOR gates or NAND gates. Followed by "what are minimum number of NAND gates required for this particular design" and it goes on.

Sometimes it starts with designing a small block. Then you wil…

First Things First -- Preparing a Good Resume

As the title says first things first, it’s very important to have good and attractive resume to get an interview call or to get shortlisted. It is always advised to start writing your own resume from scratch instead of copying/following someone else's content or template. So here are some points you should keep in mind before start writing your resume.
Most of the times your resume will be first reviewed and shortlisted by HR officers, who rarely have technical knowledge, they just look for some keywords provided by the technical manager. Keywords like Verilog, Tools names, years of experience, etc.The reviewer usually takes less than 5 minutes (or 3 minutes) to go through your resume, so make it concise.Resume should not (or never) be greater than two pages. Don't try to act smart by using small/tiny font sizes.First page should present your best qualities. It’s not like you start low and finish high, in resume you have to always start HIGH.Don't make a fancy or colourful …

Digital Design Interview Questions - All in 1

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)?

2. Implement an 2-input AND gate using a 2x1 mux.

3. What is a multiplexer?

A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output.

4. What is a ring counter?

A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on.

5. Compare and Contrast Synchronous and Asynchronous reset.

Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for small reset gl…

Digital Design Interview Questions - 6

1. What is DeMorgan's theorem?

For N variables, DeMorgan’s theorems are expressed in the following formulas:
(ABC..N)' = A' + B' + C' + ... + N' -- The complement of the product is equivalent to the sum of the complements.
(A + B + C + ... + N)' = A'B'C'...N' -- The complement of the sum is equivalent to the product of the complements.
This relationship so induced is called DeMorgan's duality.

2. F'(A, B, C, D) = C'D + ABC' + ABCD + D. Express F in Product of Sum form.

Complementing both sides and applying DeMorgan's Theorem:
F(A, B, C, D) = (C + D')(A' + B' + C)(A' + B' + C' + D')(D')

3. How many squares/cells will be present in the k-map of F(A, B, C)?

F(A, B, C) has three variables/inputs.
Therefore, number of squares/cells in k-map of F = 2(Number of variables) = 23 = 8.

4. Simplify F(A, B, C, D) = Σ ( 0, 1, 4, 5, 7, 8, 9, 12, 13)

The four variable k-map of the given express…

Boolean Expression Simplification

The k-map Method

The "Karnaugh Map Method", also known as k-map method, is popularly used to simplify Boolean expressions. The map method is first proposed by Veitch and then modified by Karnaugh, hence it is also known as "Veitch Diagram". The map is a diagram made up of squares (equal to 2 power number of inputs/variables). Each square represents a minterm, hence any Boolean expression can be represented graphically using a k-map.

The above diagram shows two (I), three (II) and four (III) variable k-maps. The number of squares is equal 2 power number of variables. Two adjacent squares will differ only by one variable. The numbers inside the squares are shown for understanding purpose only. The number shown corresponds to a minterm in the the Boolean expression.

Simplification using k-map:
Obtain the logic expression in canonical form.Identify all the minterms that produce an output of logic level 1 and place 1 in appropriate k-map cell/square. All others cells must c…