Synchronous Reset VS Asynchronous Reset

Why Reset?

A Reset is required to initialize a hardware design for system operation and to force an ASIC into a known state for simulation.

A reset simply changes the state of the device/design/ASIC to a user/designer defined state. There are two types of reset, what are they? As you can guess them, they are Synchronous reset and Asynchronous reset.

Synchronous Reset

A synchronous reset signal will only affect or reset the state of the flip-flop on the active edge of the clock. The reset signal is applied as is any other input to the state machine.

Advantages:

  • The advantage to this type of topology is that the reset presented to all functional flip-flops is fully synchronous to the clock and will always meet the reset recovery time.
  • Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant.
  • Synchronous resets provide some filtering for the reset signal such that it is not effected by glitches, unless they occur right at the clock edge. A synchronous reset is recommended for some types of designs where the reset is generated by a set of internal conditions. As the clock will filter the logic equation glitches between clock edges.
Disadvantages:
  • The problem in this topology is with reset assertion. If the reset signal is not long enough to be captured at active clock edge (or the clock may be slow to capture the reset signal), it will result in failure of assertion. In such case the design needs a pulse stretcher to guarantee that a reset pulse is wide enough to be present during the active clock edge.
  • Another problem with synchronous resets is that the logic synthesis cannot easily distinguish the reset signal from any other data signal. So proper care has to be taken with logic synthesis, else the reset signal may take the fastest path to the flip-flop input there by making worst case timing hard to meet.
  • In some power saving designs the clocked is gated. In such designed only asynchronous reset will work.
  • Faster designs that are demanding low data path timing, can not afford to have extra gates and additional net delays in the data path due to logic inserted to handle synchronous resets.
Asynchronous Reset

An asynchronous reset will affect or reset the state of the flip-flop asynchronously i.e. no matter what the clock signal is. This is considered as high priority signal and system reset happens as soon as the reset assertion is detected.

Advantages:
  • High speeds can be achieved, as the data path is independent of reset signal.
  • Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present.
  • As in synchronous reset, no work around is required for logic synthesis.
Disadvantages:
  • The problem with this type of reset occurs at logic de-assertion rather than at assertion like in synchronous circuits. If the asynchronous reset is released (reset release or reset removal) at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable.
  • Spurious resets can happen due to reset signal glitches.
Conclusion

Both types of resets have positives and negatives and none of them assure fail-proof design. So there is something called "Asynchronous assertion and Synchronous de-assertion" reset which can be used for best results. (which will be discussed in next post).

VLSI Interview Questions with Answers - 1

1. Why does the present VLSI circuits use MOSFETs instead of BJTs?
Answer


2. What are the various regions of operation of MOSFET? How are those regions used?
Answer

3. What is threshold voltage?
Answer

4. What does it mean "the channel is pinched off"?
Answer

5. Explain the three regions of operation of a MOSFET.
Answer

6. What is channel-length modulation?
Answer

7. Explain depletion region.
Answer

8. What is body effect?
Answer

9. Give various factors on which threshold voltage depends.
Answer

10. Give the Cross-sectional diagram of the CMOS.
Answer

Type-3: Give Verilog/VHDL code ...

Most Common Interview Questions: Type-3: Give Verilog/VHDL code ...

The prime intention of the interviewer in asking this question is to see the hands-on experience you have. If you have mentioned that you are familiar with Verilog/VHDL in your resume and attending an ASIC engineer post, then you can expect this question. This question usually comes after asking Type-1 and/or Type-2 questions (explained in previous posts). No interviewer starts with this type of question.

The common strategy followed is: initially you will be asked "Type-1: Design a ..." and then as an extension you will be asked to code it in Verilog or VHDL. Further, the interviewer may specifically ask you, to code for synthesis.

Tips

  • This question is asked to test your ability to code. Don't ever write a psuedo code or a code with syntax error(s).
  • Prepare for this question by coding some basic programs like flip-flops, counters, small FSMs etc. Make sure that you touch most of the commonly used Verilog/VHDL keywords.
  • Once you write some code, try to synthesize it and also try to find out the solution(s) if there are any errors.
  • Code some combinational and sequential codes. Try to code using hierarchies.
This is not a good way of testing one's knowledge, this is usually used to just see the hands-on experience you got. Sometimes this may become crucial if the project (which you are hired for) requires an ASIC design enginner urgently, so if you have enough experience then time can be saved by skipping training.

You might also want to read the following articles

Type-2: Tell us about a design/project you worked on

Type-1: Design a ...

First Things First -- Preparing a Good Resume

Type-2: Tell us about a design/project you worked on

Most Common Interview Questions: Type-2: Tell us about a design/project you worked on

Prepare for answering this question in any interview you attend, its kind of inevitable. Usually our resumes will be flooded with some projects. So an interviewer, instead of asking about one of those projects, he simply hits the ball into your court by asking this question. In general, interviewers ask to talk about your best work, it could be a design you made out of your interest or a project or part of a coursework. Irrespective of whether interviewer uses the word best its implied that you are going to talk about your best work! Now the ball is in your court you have to give a smart reply using your skills.

How to answer this question?

Remember that the time you have to answer this is limited. So instead of explaining every aspect of your design in detail, give glimpses of your design. Start taking about the best or challenging part of your design. This is best way of extracting some questions from interview which you can answer with ease. While you are explaining, the interviewer will most probably interrupt you and ask "why did you use this particular method? why not some other method?". In this case you are expected to give advantages of your design choice has, over other strategies. Failing to answer such questions will result in a very bad impression and ultimately rejection.

Example: Why did you use gray encoding for representing your FSM states? why not one-hot encoding? ... Here you have to know about one-hot encoding and the advantages that gray encoding has w.r.t. your design. If you are smart enough you can say that I considered various encoding techniques and chosen the best suited for my design. Don't forget to justify your statement. On the flip side if you say that I don't know one-hot encoding, the interviewer feels that your knowledge is limited and may also think that you have blindly followed your guides' instructions to use gray encoding.

Why is this question very important?

You should realize that you are just going to present something you already DID. In other questions you may require some time to think, solve or understand and you may get little tensed if you don't get a proper idea. But nothing like that in this question. As I said above the ball is in court and you should not make an unforced error!

All you have to do is use this question as your prime weapon to get the job!

You might also want to read the following articles

Type-1: Design a ...

First Things First -- Preparing a Good Resume

Type-1: Design a ...

Most Common Interview Questions: Type-1: Design a ...

This is the most common question one will face in his/her interview, probably the first question which starts testing your knowledge. (I mean this comes after introduction and "Tell us about yourself"). This is a lethal weapon used by the interviewer to test one's abilities: both weak and strong points. The concepts required for solving the problem are generally related to the type of job you are being tested for.

The most popular strategy used by the interview in this question is gradual increase in the complexity of the question. It goes like this ... Interviewer states the specifications of the design. You can present as simple/straight forward/redundant answer as possible. The next question could be redesign using only NOR gates or NAND gates. Followed by "what are minimum number of NAND gates required for this particular design" and it goes on.

Sometimes it starts with designing a small block. Then you will be asked to embed this module in a bigger picture and analyze the scenario. Where most likely you will face questions like "can the design (you made) be optimized for better performance of the entire module?" or "what drawbacks you see in your design when embedded in the bigger module". Basically tests how good you are with designs with a hierarchy.

Another way is step by step removal of assumptions that make the design complex as we go further.

Tips

  • Read the job description, think of possible questions or target areas, and prepare for the same.
  • ASIC interviews (especially freshers) expect a question dealing timing analysis, synthesis related issues, etc.

First Things First -- Preparing a Good Resume

As the title says first things first, it’s very important to have good and attractive resume to get an interview call or to get shortlisted. It is always advised to start writing your own resume from scratch instead of copying/following someone else's content or template. So here are some points you should keep in mind before start writing your resume.

  • Most of the times your resume will be first reviewed and shortlisted by HR officers, who rarely have technical knowledge, they just look for some keywords provided by the technical manager. Keywords like Verilog, Tools names, years of experience, etc.
  • The reviewer usually takes less than 5 minutes (or 3 minutes) to go through your resume, so make it concise.
  • Resume should not (or never) be greater than two pages. Don't try to act smart by using small/tiny font sizes.
  • First page should present your best qualities. It’s not like you start low and finish high, in resume you have to always start HIGH.
  • Don't make a fancy or colourful resume, keep it strictly professional, use formal fonts like Verdana, Time New Roman, etc. Importantly, maintain proper alignment (not zigzag).
  • Contact details: phone number and personal email-id are sufficient. Write them in the first page of the resume - after the name or in the header (top right corner).

First Page
: Name, Summary, Skills, Work Experience, Education

Name: Write your full name.

Summary: First page should present your best qualities. Start with a summary of your profile which should give an idea about your number of years of work experience, the key skills you possess and the type of job you are looking for. Summary is usually 2-3 lines long. Use simple language, no need to be bombastic.

Skills include programming languages or HDLs, Technologies known, familiar Tools, etc. If you have a very basic knowledge in something say VHDL, then it is recommended not to mention it. If you think it's really helps to include it then you may write something in brackets like "VHDL (beginner)". I have seen many people writing this: "Operating systems: DOS, Windows 98/2000/XP, Linux", mentioning OS in resume has a wrong understanding by many. It doesn't mean that you used that particular OS, it means that you know "how that particular OS works", like its design, properties, merits, limitations, uses etc. If you just know how to create/delete a file or how to use some commands on OS, then don't mention it.

Work Experience: For each company you worked in (including current company), mention your designation, company name, location and period. You can include any internship(s) you did, just say "summer intern" or similar thing as the designation. Always write the list in chronological order from latest to oldest.

Education: Mention two or three latest levels of education you attended like "Masters and Bachelors" or "Masters, Bachelors and Class XII" or etc. As your work experience keeps increasing, the significance of this section keeps coming down. A fresher or less than 2 years experienced candidate will definitely place this section in first page.

If you still have some space left, then write about your publications. If you don't have any research papers then start writing about your projects.


Second Page
: Projects, Honors/Achievements, Personal information,

Projects: List 3-5 best projects you did, in chronological order. Give title, location, period, Technologies used and abstract. Restrict abstract to 4 (or may be 5 if you have space) lines. Don't write everything about the project in resume, so that the interviewer may ask you some questions about it, which by the way should be an advantage. As you expect this scenario, you will prepare and will feel confident and comfortable in the interview. Most likely you will be able to give nice explanation and impress the interviewer.

Honors/Achievements: Enumerate all the honors like scholarships, awards, prizes etc.

Personal information: Contact information, Languages known, etc.

This is a general way of writing a resume, there is no hard and fast rule/template that you should follow the one given above. One always has the liberty to prepare a resume as he/she likes it. But once you are done check whether you will shortlist your own resume if you are the person who is reviewing it!

Last but the not the least, always perform a word to word spell check manually. Don't trust MS-Word or some other spell check software. Also get it reviewed by your friends and colleagues.

Digital Design Interview Questions - All in 1

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)?
Answer


2. Implement an 2-input AND gate using a 2x1 mux.
Answer

3. What is a multiplexer?
Answer

4. What is a ring counter?
Answer

5. Compare and Contrast Synchronous and Asynchronous reset.
Answer

6. What is a Johnson counter?
Answer

7. An assembly line has 3 fail safe sensors and one emergency shutdown switch.The line should keep moving unless any of the following conditions arise:
(1) If the emergency switch is pressed
(2) If the senor1 and sensor2 are activated at the same time.
(3) If sensor 2 and sensor3 are activated at the same time.
(4) If all the sensors are activated at the same time
Suppose a combinational circuit for above case is to be implemented only with NAND Gates. How many minimum number of 2 input NAND gates are required?
Answer

8. In a 4-bit Johnson counter How many unused states are present?
Answer

9. Design a 3 input NAND gate using minimum number of 2 input NAND gates.
Answer

10. How can you convert a JK flip-flop to a D flip-flop?
Answer

11. What are the differences between a flip-flop and a latch?
Answer

12. What is the difference between Mealy and Moore FSM?
Answer

13. What are various types of state encoding techniques? Explain them.
Answer

14. Define Clock Skew , Negative Clock Skew, Positive Clock Skew.
Answer

15. Give the transistor level circuit of a CMOS NAND gate.
Answer

16. Design a 4-bit comparator circuit.
Answer

17. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR (without inverting the output)?
Answer

18. Define Metastability.
Answer

19. Compare and contrast between 1's complement and 2's complement notation.
Answer

20. Give the transistor level circuit of CMOS, nMOS, pMOS, and TTL inverter gate.
Answer

21. What are set up time and hold time constraints?
Answer

22. Give a circuit to divide frequency of clock cycle by two.
Answer

23. Design a divide-by-3 sequential circuit with 50% duty circle.
Answer

24. Explain different types of adder circuits.
Answer

25. Give two ways of converting a two input NAND gate to an inverter.
Answer

26. Draw a Transmission Gate-based D-Latch.
Answer

27. Design a FSM which detects the sequence 10101 from a serial line without overlapping.
Answer

28. Design a FSM which detects the sequence 10101 from a serial line with overlapping.
Answer

29. Give the design of 8x1 multiplexer using 2x1 multiplexers.
Answer

30. Design a counter which counts from 1 to 10 ( Resets to 1, after 10 ).
Answer

31. Design 2 input AND, OR, and EXOR gates using 2 input NAND gate.
Answer

32. Design a circuit which doubles the frequency of a given input clock signal.
Answer

33. Implement a D-latch using 2x1 multiplexer(s).
Answer

34. Give the excitation table of a JK flip-flop.
Answer

35. Give the Binary, Hexadecimal, BCD, and Excess-3 code for decimal 14.
Answer

36. What is race condition?
Answer

37. Give 1's and 2's complement of 19.
Answer

38. Design a 3:6 decoder.
Answer

39. If A*B=C and C*A=B then, what is the Boolean operator * ?
Answer

40. Design a 3 bit Gray Counter.
Answer

41. Expand the following: PLA, PAL, CPLD, FPGA.
Answer

42. Implement the functions: X = A'BC + ABC + A'B'C' and Y = ABC + AB'C using a PLA.
Answer

43. What are PLA and PAL? Give the differences between them.
Answer

44. What is LUT?
Answer

45. What is the significance of FPGAs in modern day electronics? (Applications of FPGA.)
Answer

46. What are the differences between CPLD and FPGA.
Answer

47. Compare and contrast FPGA and ASIC digital designing.
Answer

48. Give True or False.
(a) CPLD consumes less power per gate when compared to FPGA.
(b) CPLD has more complexity than FPGA
(c) FPGA design is slower than corresponding ASIC design.
(d) FPGA can be used to verify the design before making a ASIC.
(e) PALs have programmable OR plane.
(f) FPGA designs are cheaper than corresponding ASIC, irrespective of design complexity.
Answer

49. Arrange the following in the increasing order of their complexity: FPGA,PLA,CPLD,PAL.
Answer

50. Give the FPGA digital design cycle.
Answer

51. What is DeMorgan's theorem?
Answer

52. F'(A, B, C, D) = C'D + ABC' + ABCD + D. Express F in Product of Sum form.
Answer

53. How many squares/cells will be present in the k-map of F(A, B, C)?
Answer

54. Simplify F(A, B, C, D) = S ( 0, 1, 4, 5, 7, 8, 9, 12, 13)
Answer

55. Simplify F(A, B, C) = S (0, 2, 4, 5, 6) into Product of Sums.
Answer

56. The simplified expression obtained by using k-map method is unique. True or False. Explain your answer.
Answer

57. Give the characteristic tables of RS, JK, D and T flip-flops.
Answer

58. Give excitation tables of RS, JK, D and T flip-flops.
Answer

59. Design a BCD counter with JK flip-flops
Answer

60. Design a counter with the following binary sequence 0, 1, 9, 3, 2, 8, 4 and repeat. Use T flip-flops.
Answer

Digital Design Interview Questions - 6

1. What is DeMorgan's theorem?
Answer


2. F'(A, B, C, D) = C'D + ABC' + ABCD + D. Express F in Product of Sum form.
Answer

3. How many squares/cells will be present in the k-map of F(A, B, C)?
Answer

4. Simplify F(A, B, C, D) = Σ ( 0, 1, 4, 5, 7, 8, 9, 12, 13)
Answer

5. Simplify F(A, B, C) = Σ (0, 2, 4, 5, 6) into Product of Sums.
Answer

6. The simplified expression obtained by using k-map method is unique. True or False. Explain your answer.
Answer

7. Give the characteristic tables of RS, JK, D and T flip-flops.
Answer

8. Give excitation tables of RS, JK, D and T flip-flops.
Answer

9. Design a BCD counter with JK flip-flops
Answer

10. Design a counter with the following binary sequence 0, 1, 9, 3, 2, 8, 4 and repeat. Use T flip-flops.
Answer

Boolean Expression Simplification

The k-map Method

The "Karnaugh Map Method", also known as k-map method, is popularly used to simplify Boolean expressions. The map method is first proposed by Veitch and then modified by Karnaugh, hence it is also known as "Veitch Diagram". The map is a diagram made up of squares (equal to 2 power number of inputs/variables). Each square represents a minterm, hence any Boolean expression can be represented graphically using a k-map.


The above diagram shows two (I), three (II) and four (III) variable k-maps. The number of squares is equal 2 power number of variables. Two adjacent squares will differ only by one variable. The numbers inside the squares are shown for understanding purpose only. The number shown corresponds to a minterm in the the Boolean expression.

Simplification using k-map:

  • Obtain the logic expression in canonical form.
  • Identify all the minterms that produce an output of logic level 1 and place 1 in appropriate k-map cell/square. All others cells must contain a 0.
  • Every square containing 1 must be considered at least once.
  • A square containing 1 can be included in as many groups as desired.
  • There can be isolated 1's, i.e. which cannot be included in any group.
  • A group must be as large as possible. The number of squares in a group must be a power of 2 i.e. 2, 4, 8, ... so on.
  • The map is considered to be folded or spherical, therefore squares at the end of a row or column are treated as adjacent squares.
The simplest Boolean expression contains minimum number of literals in any one in sum of products or products of sum. The simplest form obtained is not necessarily unique as grouping can be made in different ways.

Valid Groups

The following diagram illustrates the valid grouping k-map method.


Simplification: Product of Sums

The above method gives a simplified expression in Sum of Products form. With slight modification to the above method, we can get the simplified expression in Product of Sums form. Group adjacent 0's instead of 1's, which gives us the complement of the function i.e. F'. The complement of obtained F' gives us the required expression F, which is done using the DeMorgan's theorem. See Example-2 below for better understanding.

Examples:

1. Simplify F(A, B, C) = Σ (0, 2, 4, 5, 6).

The three variable k-map of the given expression is:


The grouping is also shown in the diagram. Hence we get,
F(A, B, C) = AB' + C'


2. Simplify F(A, B, C) = Σ (0, 2, 4, 5, 6) into Product of Sums.

The three variable k-map of the given expression is:


The 0's are grouped to get the F'.
F' = A'C + BC

Complementing both sides and using DeMorgan's theorem we get F,
F = (A + C')(B' + C')


3. Simplify F(A, B, C, D) = Σ( 0, 1, 4, 5, 7, 8, 9, 12, 13)


The four variable k-map of the given expression is:


The grouping is also shown in the diagram. Hence we get,
F(A, B, C, D) = C' + A'BD

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