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Introduction to SystemVerilog


SystemVerilog is a combined hardware description language (HDL) and hardware verification language (HVL) based on extensions to Verilog HDL.

SystemVerilog as a RTL design language is an extension of Verilog HDL containing all features of Verilog. As a verification language SystemVerilog uses object-oriented programming (OOP) techniques similar to that of C++, Java etc. Clearly, the main advantage of SystemVerilog is the unification of HDL and HVL, that provides a single platform for RTL design and verification.

As a HDL SystemVerilog supports C/C++ like features including typedef, struct, union, enum, etc. These new features can be used for faster and efficient implementation of HDL, increasing the productivity of RTL design process. However, SystemVerilog’s strongest suite comes as a HVL.  It provides a complete verification environment supporting constraint random generation, assertion based verification and coverage driven verification.

Some of the SystemVerilog featu…

XMR: Cross Module Reference

Cross Module Reference

Cross Module Reference abbreviated as XMR is a very useful concept in Verilog HDL (as well as system Verilog). However it seems to be less known among many users of Verilog.
XMR is a mechanism built into Verilog to globally reference (i.e., across the modules) to any nets, tasks, functions etc. Using XMR, one can refer to any object of a module in any other module, irrespective of whether they are present below or above its hierarchy. Hence, a XMR can be a: Downward reference ORUpward reference
Consider the following hierarchy: Module ANet xInstance P of Module BNet xInstance M of Module DNet xInstance Q of Module CNet xInstance N of Module E  Net xInstance R of Module BNet xInstance M of Module DNet x
In test bench: Instance top of Module A
In the above scenario, there is a net named x in all modules. Using XMR each x can be globally referenced anywhere within the test bench hierarchy as follows. top.xtop.P.xt…

Synchronous Reset vs. Asynchronous Reset

Why Reset?

A Reset is required to initialize a hardware design for system operation and to force an ASIC into a known state for simulation.

A reset simply changes the state of the device/design/ASIC to a user/designer defined state. There are two types of reset, what are they? As you can guess them, they are Synchronous reset and Asynchronous reset.

Synchronous Reset

A synchronous reset signal will only affect or reset the state of the flip-flop on the active edge of the clock. The reset signal is applied as is any other input to the state machine.

The advantage to this type of topology is that the reset presented to all functional flip-flops is fully synchronous to the clock and will always meet the reset recovery time.Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant…

VLSI Interview Questions with Answers - 1

1. Why does the present VLSI circuits use MOSFETs instead of BJTs?

Compared to BJTs, MOSFETs can be made very small as they occupy very small silicon area on IC chip and are relatively simple in terms of manufacturing. Moreover digital and memory ICs can be implemented with circuits that use only MOSFETs i.e. no resistors, diodes, etc.

2. What are the various regions of operation of MOSFET? How are those regions used?

MOSFET has three regions of operation: the cut-off region, the triode region, and the saturation region.
The cut-off region and the triode region are used to operate as switch. The saturation region is used to operate as amplifier.

3. What is threshold voltage?

The value of voltage between Gate and Source i.e. VGS at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called threshold voltage (Vt is positive for NMOS and negative for PMOS).

4. What does it mean "the channel is pinched off"?

Type-3: Give Verilog/VHDL code ...

Most Common Interview Questions: Type-3: Give Verilog/VHDL code ...

The prime intention of the interviewer in asking this question is to see the hands-on experience you have. If you have mentioned that you are familiar with Verilog/VHDL in your resume and attending an ASIC engineer post, then you can expect this question. This question usually comes after asking Type-1 and/or Type-2 questions (explained in previous posts). No interviewer starts with this type of question.

The common strategy followed is: initially you will be asked "Type-1: Design a ..." and then as an extension you will be asked to code it in Verilog or VHDL. Further, the interviewer may specifically ask you, to code for synthesis.

This question is asked to test your ability to code. Don't ever write a psuedo code or a code with syntax error(s).Prepare for this question by coding some basic programs like flip-flops, counters, small FSMs etc. Make sure that you touch most of the commonly used Verilog/VH…

Type-2: Tell us about a design/project you worked on

Most Common Interview Questions: Type-2: Tell us about a design/project you worked on

Prepare for answering this question in any interview you attend, its kind of inevitable. Usually our resumes will be flooded with some projects. So an interviewer, instead of asking about one of those projects, he simply hits the ball into your court by asking this question. In general, interviewers ask to talk about your best work, it could be a design you made out of your interest or a project or part of a coursework. Irrespective of whether interviewer uses the word best its implied that you are going to talk about your best work! Now the ball is in your court you have to give a smart reply using your skills.

How to answer this question?

Remember that the time you have to answer this is limited. So instead of explaining every aspect of your design in detail, give glimpses of your design. Start taking about the best or challenging part of your design. This is best way of extracting some questions fro…