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Verilog Interview Questions - 3

1. How are blocking and non-blocking statements executed?
Answer

2. How do you model a synchronous and asynchronous reset in Verilog?
Answer

3. What happens if there is connecting wires width mismatch?
Answer

4. What are different options that can be used with $display statement in Verilog?
Answer

5. Give the precedence order of the operators in Verilog.
Answer

6. Should we include all the inputs of a combinational circuit in the sensitivity list? Give reason.
Answer

7. Give 10 commonly used Verilog keywords.
Answer

8. Is it possible to optimize a Verilog code such that we can achieve low power design?
Answer

9. How does the following code work?
wire [3:0] a;
always @(*)
begin
case (1'b1)
 a[0]: $display("Its a[0]");
 a[1]: $display("Its a[1]");
 a[2]: $display("Its a[2]");
 a[3]: $display("Its a[3]");
 default: $display("Its default")
endcase
end
Answer

10. Which is updated first: signal or variable?
Answer
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