Digital Design Interview Questions - 4

1. Design 2 input AND, OR, and EXOR gates using 2 input NAND gate.
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2. Design a circuit which doubles the frequency of a given input clock signal.
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3. Implement a D-latch using 2x1 multiplexer(s).
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4. Give the excitation table of a JK flip-flop.
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5. Give the Binary, Hexadecimal, BCD, and Excess-3 code for decimal 14.
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6. What is race condition?
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7. Give 1's and 2's complement of 19.
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8. Design a 3:6 decoder.
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9. If A*B=C and C*A=B then, what is the Boolean operator * ?
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10. Design a 3 bit Gray Counter.
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7 Comments:

Anonymous said...

really good, all concepts at a glamce..i like it..very useful/

jyotsna said...

Only-VLSI is superb!!!!!!!!!!!!!!!!!!!!!!!!!

Anonymous said...

superb keep it up

Anonymous said...

but latch wont get triggered on edges so will it work by taking clock as selective signal

Ramesh said...
This comment has been removed by the author.
Ramesh said...

For Q9, * boolean operator could be XNOR too.

manish kundu said...

this is for comment posted on feb 13,,
see clock can be edge trigerred as well as level trigerred, we all knw that Mux requires a selective signal but here tge requirement is latch and basic building block is Mux, so dear u have to implement Latch using mux and the ports will be declared with the port names of latches. and By the way latches do have clocks as it is a sequential device.

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