Verilog Interview Questions - 1

Questions are related to comparison (What is the difference betweem ...).

1. What is the difference between a function and a task?
Answer

Functions	Tasks
Can enable another function but not another task.	Can enable other tasks and functions.
Executes in 0 simulation time.	May execute in non-zero simulation time.
Must not contain any delay, event, or timing control statements.	May contain delay, event, or timing control statements.
Must have at least one input argument. They can have more than one input.	May have zero or more arguments of type input, output, or inout.
Functions always return a single value. They cannot have output or inout arguments.	Tasks do not return with a value, but can pass multiple values through output and inout arguments.

2. What is the difference between $display and $monitor?
Answer

The syntax of both statements is same. $monitor continuously monitors the values of the variables or signals specified in the parameter list and executes the statement whenever the value of any one of the variable/parameter changes. Unlike $display, $monitor needs to be invoked only once.

3. What is the difference between wire and reg?
Answer

Wire is a net data type, represents connections between hardware elements. It's default value is z. Where as reg is a register data type, which represent data storage elements. Registers retain value until another value is placed onto them. It's default value is x.

4. What is the difference between blocking and non-blocking assignments?
Answer

Blocking assignment statements are executed in the order they are specified in a sequential block. A blocking assignment will not block execution of statements that follow in a parallel block. The " = " operator is used to specify blocking assignments.
Nonblocking assignments allow scheduling of assignments without blocking execution of the statements that follow in a sequential block. A " <= " operator is used to specify nonblocking assignments.

5. What is the difference between casex, casez and case statements?
Answer

casez treats all z values in the case expression as don't cares. casex treats all x and z values in the case expression as don't cares.

6. What is the difference between transport delay and inertial delay?
Answer

Transport delay is the delay caused by the wires connecting the gates. Wire do delay the signal they carry, this is due to the wire resistance, capacitance, and inductance. Simply transport delay is propagation delay on a wire. In verilog transport delay is modeled as follows:
a <= #10 b; Inertial delay is the time taken by a gate to change its output. It is the gate delay. In verilog inertial delay is modeled as follows: assign #10 a = b;

7. What is the difference between unary and logical operators?
Answer

Unary operators have only one operand, where as logical operators are of two operands.

8. What is the difference between compiled, interpreted, event based and cycle based simulators?
Answer

9. What is the difference between ( = = , ! = ) and ( = = = , ! = = )?
Answer

The equality operators ( = = , ! = ) will yield an x if either operand has x or z in its bits. Where as the case equality operators ( = = = , ! = = ) compare both operands bit by bit and compare all bits, including x and z.

10. What are the difference between Verilog and VHDL?
Answer

Verilog is similar to C programming language (syntactically) and VHDL is similar to ADA. Verilog is simple to learn and simple to write code where as VHDL takes longer time to learn and is bit complicated when it comes to write codes. Verilog supports lower level logic representation as well (transistor level) where as VHDL does not.