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Most Common Interview Questions: Type-1: Design a ... This is the most common question one will face in his/her interview, probably the first question which starts testing your knowledge. (I mean this comes after introduction and "Tell us about yourself"). This is a lethal weapon used by the interviewer to test one's abilities: both weak and strong points. The concepts required for solving the problem are generally related to the type of job you are being tested for. The most popular strategy used by the interview in this question is gradual increase in the complexity of the question . It goes like this ... Interviewer states the specifications of the design. You can present as simple/straight forward/redundant answer as possible. The next question could be redesign using only NOR gates or NAND gates. Followed by "what are minimum number of NAND gates required for this particular design" and it goes on. Sometimes it starts with designing a small block. Then you ...

As the title says first things first, it’s very important to have good and attractive resume to get an interview call or to get shortlisted. It is always advised to start writing your own resume from scratch instead of copying/following someone else's content or template. So here are some points you should keep in mind before start writing your resume. Most of the times your resume will be first reviewed and shortlisted by HR officers, who rarely have technical knowledge, they just look for some keywords provided by the technical manager. Keywords like Verilog, Tools names, years of experience, etc. The reviewer usually takes less than 5 minutes (or 3 minutes) to go through your resume, so make it concise. Resume should not (or never) be greater than two pages . Don't try to act smart by using small/tiny font sizes. First page should present your best qualities. It’s not like you start low and finish high, in resume you have to always start HIGH. Don't make a fancy or colou...

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)? Answer 2. Implement an 2-input AND gate using a 2x1 mux. Answer 3. What is a multiplexer? Answer A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output. 4. What is a ring counter? Answer A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on. 5. Compare and Contrast Synchronous and Asynchronous reset. Answer Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for sma...

1. What is DeMorgan's theorem? Answer For N variables, DeMorgan’s theorems are expressed in the following formulas: (ABC..N)' = A' + B' + C' + ... + N' -- The complement of the product is equivalent to the sum of the complements. (A + B + C + ... + N)' = A'B'C'...N' -- The complement of the sum is equivalent to the product of the complements. This relationship so induced is called DeMorgan's duality. 2. F'(A, B, C, D) = C'D + ABC' + ABCD + D. Express F in Product of Sum form. Answer Complementing both sides and applying DeMorgan's Theorem: F(A, B, C, D) = (C + D')(A' + B' + C)(A' + B' + C' + D')(D') 3. How many squares/cells will be present in the k-map of F(A, B, C)? Answer F(A, B, C) has three variables/inputs. Therefore, number of squares/cells in k-map of F = 2 (Number of variables) = 2 3 = 8. 4. Simplify F(A, B, C, D) = Σ ( 0, 1, 4, 5, 7, 8, 9, 12, 13) Answer The four variable k-map o...

The k-map Method The "Karnaugh Map Method", also known as k-map method, is popularly used to simplify Boolean expressions. The map method is first proposed by Veitch and then modified by Karnaugh, hence it is also known as "Veitch Diagram". The map is a diagram made up of squares (equal to 2 power number of inputs/variables). Each square represents a minterm, hence any Boolean expression can be represented graphically using a k-map. The above diagram shows two (I), three (II) and four (III) variable k-maps. The number of squares is equal 2 power number of variables. Two adjacent squares will differ only by one variable. The numbers inside the squares are shown for understanding purpose only. The number shown corresponds to a minterm in the the Boolean expression. Simplification using k-map : Obtain the logic expression in canonical form. Identify all the minterms that produce an output of logic level 1 and place 1 in appropriate k-map cell/square. All others cells m...

Definition A machine consisting of a set of states, a start state, an input, and a transition function that maps input and current states to a next state. Machine begins in the start state with an input. It changes to new states depending on the transition function. The transition function depends on current states and inputs. The output of the machine depends on input and/or current state. There are two types of FSMs which are popularly used in the digital design. They are Moore machine Mealy machine Moore machine In Moore machine the output depends only on current state.The advantage of the Moore model is a simplification of the behavior. Mealy machine In Mealy machine the output depend on both current state and input.The advantage of the Mealy model is that it may lead to reduction of the number of states. In both models the next state depends on current state and input. Some times designers use mixed models. States will be encoded for representing a particular state. Representatio...

Designing a FSM is the most common and challenging task for every digital logic designer. One of the key factors for optimizing a FSM design is the choice of state coding, which influences the complexity of the logic functions, the hardware costs of the circuits, timing issues, power usage, etc. There are several options like binary encoding, gray encoding, one-hot encoding, etc. The choice of the designer depends on the factors like technology, design specifications, etc. One-hot encoding In one-hot encoding only one bit of the state vector is asserted for any given state. All other state bits are zero. Thus if there are n states then n state flip-flops are required. As only one bit remains logic high and rest are logic low, it is called as One-hot encoding. Example : If there is a FSM, which has 5 states. Then 5 flip-flops are required to implement the FSM using one-hot encoding. The states will have the following values: S0 - 10000 S1 - 01000 S2 - 00100 S3 - 00010 S4 - 00001 Adv...