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Showing posts from March, 2008

1. Design 2 input AND, OR, and EXOR gates using 2 input NAND gate.

2. Design a circuit which doubles the frequency of a given input clock signal.

3. Implement a D-latch using 2x1 multiplexer(s).

4. Give the excitation table of a JK flip-flop.

5. Give the Binary, Hexadecimal, BCD, and Excess-3 code for decimal 14.

14:
Binary: 1110
BCD: 0001 0100
Excess-3: 10001

6. What is race condition?

7. Give 1's and 2's complement of 19.

19: 10011
1's complement: 01100
2's complement: 01101

8. Design a 3:6 decoder.

9. If A*B=C and C*A=B then, what is the Boolean operator * ?

* is Exclusive-OR.

10. Design a 3 bit Gray Counter.

1. How are blocking and non-blocking statements executed?

In a blocking statement, the RHS will be evaluated and the LHS will be then updated, without interruption from any other Verilog statement. A blocking statement "blocks" trailing statements.
In a non-blocking statement, RHS will be evaluated at the beginning of the time step. Then the LHS will be updated at the end of the time step.

2. How do you model a synchronous and asynchronous reset in Verilog?

Synchronous reset:
always @(posedge clk)
begin
--
if(reset)
--
end

Asynchronous reset:
always @(posedge clk or posedge reset)
begin
--
if(reset)
--
end
The logic is very simple: In asynchronous reset, the always block will invoked at positive edge of the reset signal, irrespective of clock's value.

3. What happens if there is connecting wires width mismatch?

For example there are two signals rhs[7:0], and lhs[15:0]. If we do rhs = lhs. Then it is equivalent to rhs = lhs[7:0]. Assignment starts from LSBs of the signals,…

### VLSI Interview Questions - 5

This sections contains interview questions related to LOW POWER VLSI DESIGN.

1. What are the important aspects of VLSI optimization?

Power, Area, and Speed.
2. What are the sources of power dissipation?

+ Dynamic power consumption, due to logic transitions causing logic gates to charge/discharge load capacitance.
+ Short-circuit current, this occurs when p-tree and n-tree shorted (for a while) during logic transition.
+ Leakage current, this is a very important source of power dissipation in nano technology, it increases with decrease in lambda value. It is caused due to diode leakages around transistors and n-wells.
3. What is the need for power reduction?

Low power increases noise immunity, increases batter life, decreases cooling and packaging costs.
4. Give some low power design techniques.

Voltage scaling, transistor resizing, pipelining and parallelism, power management modes like standby modes, etc.
5. Give a disadvantage of voltage scaling technique fo…

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)?

2. Implement an 2-input AND gate using a 2x1 mux.

3. What is a multiplexer?

A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output.

4. What is a ring counter?

A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on.

5. Compare and Contrast Synchronous and Asynchronous reset.

Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for small reset gl…

### VLSI Interview Questions - 4

1. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?

To limit the height of the stack. The higher the stack the slower the gate will be. In NAND and NOR gates the number of gates present in the stack is usually same as the number of inputs plus one. So inputs are limited to four.

2. What are static and dynamic power dissipation w.r.t to CMOS gate?

3. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) considering Channel Length Modulation.

4. Which is fastest among the following technologies: CMOS, BiCMOS, TTL, ECL?

5. What is a transmission gate, and what is its typical use in VLSI?

6. Draw the cross section of nMOS or pMOS.

7. What should be done to the size of a pMOS transistor inorder to increase its threshold voltage?

8. Explain the various MOSFET Capacitances and their significance.

9. On what factors does the resistance of metal depend on?

R = (…

### VLSI Interview Questions - 3

1. Explain the voltage transfer characteristics of a CMOS Inverter.

2. What should be done to the size of a nMOS transistor in order to increase its threshold voltage?

3. What are the advantages of CMOS technology?

4. Give the expression for CMOS switching power dissipation.

Pswitching = (1/2)CVdd2/f
Where
Pswitching = Switching power.
Vdd = Supply voltage.
f = Operating frequency.

5. Why is static power dissipation very low in CMOS technology when compared to others?

6. What is velocity saturation? What are its effects?

In semiconductors, when a strong enough electric field is applied, the carrier velocity in the semiconductor reaches a maximum value. When this happens, the semiconductor is said to be in a state of velocity saturation. As the applied electric field increases from that point, the carrier velocity no longer increases.
In sub-micron technology velocity saturation is an important design characteristic. Velocity saturation grea…

### VLSI Interview Questions - 2

1. Explain the various MOSFETcapacitance and give their significance.

2. What is the fundamental difference between a MOSFET and BJT ?

In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-channel MOS) - In BJT, we see current due to both the carriers.. electrons and holes. BJT is a current controlled device and MOSFET is a voltage controlled device.

3. What is meant by scaling in VLSI design? Describe various effects of scaling.

4. What is early effect?

5. Compare and contrast analog and digital design.

6. What are various types of the number notations? Explain them.

7. Why are most interrupts active low?

If you consider the transistor level of a module, active low means the capacitor in the output terminal gets charged or discharged based on low to high and high to low transition, respectively. when it goes from high to low it depends on the pull down resistor that pulls it down and it is relatively easy for the output …

1. What are the differences between a flip-flop and a latch?

Flip-flops are edge-sensitive devices where as latches are level sensitive devices.
Flip-flops are immune to glitches where are latches are sensitive to glitches.
Latches require less number of gates (and hence less power) than flip-flops.
Latches are faster than flip-flops.

2. What is the difference between Mealy and Moore FSM?

Mealy FSM uses only input actions, i.e. output depends on input and state. The use of a Mealy FSM leads often to a reduction of the number of states.
Moore FSM uses only entry actions, i.e. output depends only on the state. The advantage of the Moore model is a simplification of the behavior.

3. What are various types of state encoding techniques? Explain them.

One-Hot encoding: Each state is represented by a bit flip-flop). If there are four states then it requires four bits (four flip-flops) to represent the current state. The valid state values are 1000, 0100, 0010, and 0001. If the value…

### VLSI Interview Questions - 1

1. How does a MOSFET works?

2. Explain various types of digital design technologies ( CMOS, TTL etc).

3. What is threshold voltage?

4. What is noise margin?

5. Explain the three modes of operation of a MOSFET.

6. What is channel-length modulation?

7. What is doping?

8. What is body effect?

9. Give various factors on which threshold voltage depends.

10. Explain nMOS and pMOS.

1. What are set up time and hold time constraints?

Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.
Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.
Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable, which is known as as metastable state or quasi stable state. At the end of metastable state, the flip-flop settles down to either logic high or logic low. This whole process is known as metastability.

2. Give a circuit to divide frequency of clock cycle by two.

3. Design a divide-by-3 sequential circuit with 50% duty circle.

4. Explain different types of adder circuits.