1. How are blocking and non-blocking statements executed?

2. How do you model a synchronous and asynchronous reset in Verilog?

3. What happens if there is connecting wires width mismatch?

4. What are different options that can be used with \$display statement in Verilog?

5. Give the precedence order of the operators in Verilog.

6. Should we include all the inputs of a combinational circuit in the sensitivity list? Give reason.

7. Give 10 commonly used Verilog keywords.

8. Is it possible to optimize a Verilog code such that we can achieve low power design?

9. How does the following code work?
wire [3:0] a;
always @(*)
begin
case (1'b1)
a[0]: \$display("Its a[0]");
a[1]: \$display("Its a[1]");
a[2]: \$display("Its a[2]");
a[3]: \$display("Its a[3]");
default: \$display("Its default")
endcase
end

10. Which is updated first: signal or variable?

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2. Implement an 2-input AND gate using a 2x1 mux.

3. What is a multiplexer?

A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output.

4. What is a ring counter?

A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on.

5. Compare and Contrast Synchronous and Asynchronous reset.

Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for small reset gl…

### Gate-Level Modeling

>> Introduction
>> Gate Primitives
>> Delays
>> Examples

Introduction

In Verilog HDL a module can be defined using various levels of abstraction. There are four levels of abstraction in verilog. They are:
Behavioral or algorithmic level: This is the highest level of abstraction. A module can be implemented in terms of the design algorithm. The designer no need to have any knowledge of hardware implementation.Data flow level: In this level the module is designed by specifying the data flow. Designer must how data flows between various registers of the design.Gate level: The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design.Switch level: This is the lowest level of abstraction. The design is implemented using switches/transistors. Designer requires the knowledge of switch-level implementation details.
Gate-level modeling is virtually the lowest-level of abstraction, because t…

### Synchronous Reset vs. Asynchronous Reset

Why Reset?

A Reset is required to initialize a hardware design for system operation and to force an ASIC into a known state for simulation.

A reset simply changes the state of the device/design/ASIC to a user/designer defined state. There are two types of reset, what are they? As you can guess them, they are Synchronous reset and Asynchronous reset.

Synchronous Reset

A synchronous reset signal will only affect or reset the state of the flip-flop on the active edge of the clock. The reset signal is applied as is any other input to the state machine.