Skip to main content

Parallel vs Serial Data Transmission

Parallel and serial data transmission are most widely used data transfer techniques. Parallel transfer have been the preferred way for transfer data. But with serial data transmission we can achieve high speed and with some other advantages.

In parallel transmission n bits are transfered simultaneously, hence we have to process each bit separately and line up them in an order at the receiver. Hence we have to convert parallel to serial form. This is known as overhead in parallel transmission.

Signal skewing is the another problem with parallel data transmission. In the parallel communication, n bits leave at a time, but may not be received at the receiver at the same time, some may reach late than others. To overcome this problem, receiving end has to synchronize with the transmitter and must wait until all the bits are received. The greater the skew the greater the delay, if delay is increased that effects the speed.

Another problem associated with parallel transmission is crosstalk. When n wires lie parallel to each, the signal in some particular wire may get attenuated or disturbed due the induction, cross coupling etc. As a result error grows significantly, hence extra processing is necessary at the receiver.

Serial communication is full duplex where as parallel communication is half duplex. Which means that, in serial communication we can transmit and receive signal simultaneously, where as in parallel communication we can either transmit or receive the signal. Hence serial data transfer is superior to parallel data transfer.

Practically in computers we can achieve 150MBPS data transfer using serial transmission where as with parallel we can go up to 133MBPS only.

The advantage we get using parallel data transfer is reliability. Serial data transfer is less reliable than parallel data transfer.
Labels:

Comments

OGEN Infosystem (P) Limited said…
Thank you so much for this interesting blog. Visit Ogen Infosystem for Website and SEO Services in Delhi, India. For more information visit our website.
Website Designing Company in India
November 2, 2020 at 9:01 PM
haseeb said…
Free Download Microsoft Office 2021 full version standalone offline installer for macOS. It's built from the bottom up to take advantage of the latest Mac . MS Office Cracken
August 1, 2022 at 11:09 AM
Post a Comment

Popular posts from this blog

Digital Design Interview Questions - All in 1

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)? Answer 2. Implement an 2-input AND gate using a 2x1 mux. Answer 3. What is a multiplexer? Answer A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output. 4. What is a ring counter? Answer A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on. 5. Compare and Contrast Synchronous and Asynchronous reset. Answer Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for sma...
223 comments
Read more

XMR: Cross Module Reference

Cross Module Reference   Cross Module Reference abbreviated as XMR is a very useful concept in Verilog HDL (as well as system Verilog). However it seems to be less known among many users of Verilog. XMR is a mechanism built into Verilog to globally reference (i.e., across the modules) to any nets, tasks, functions etc. Using XMR, one can refer to any object of a module in any other module, irrespective of whether they are present below or above its hierarchy. Hence, a XMR can be a:   Downward reference OR Upward reference   Consider the following hierarchy:     Module A   Net x   Instance P of Module B     Net x   Instance M of Module D   Net x   Instance Q of Module C   Net x   Instance N of Module E    Net x   Instance R of Module B   Net x   Instance M of Module D   Net x ...
5 comments
Read more

One-hot Encoding

Designing a FSM is the most common and challenging task for every digital logic designer. One of the key factors for optimizing a FSM design is the choice of state coding, which influences the complexity of the logic functions, the hardware costs of the circuits, timing issues, power usage, etc. There are several options like binary encoding, gray encoding, one-hot encoding, etc. The choice of the designer depends on the factors like technology, design specifications, etc. One-hot encoding In one-hot encoding only one bit of the state vector is asserted for any given state. All other state bits are zero. Thus if there are n states then n state flip-flops are required. As only one bit remains logic high and rest are logic low, it is called as One-hot encoding. Example : If there is a FSM, which has 5 states. Then 5 flip-flops are required to implement the FSM using one-hot encoding. The states will have the following values: S0 - 10000 S1 - 01000 S2 - 00100 S3 - 00010 S4 - 00001 Adv...
Post a Comment
Read more