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Setup and Hold TIme

Every flip-flop has restrictive time regions around the active clock edge in which input should not change. We call them restrictive because any change in the input in this regions the output may be the expected one (*see below). It may be derived from either the old input, the new input, or even in between the two. Here we define, two very important terms in the digital clocking. Setup and Hold time.
  • The setup time is the interval before the clock where the data must be held stable.
  • The hold time is the interval after the clock where the data must be held stable. Hold time can be negative, which means the data can change slightly before the clock edge and still be properly captured. Most of the current day flip-flops has zero or negative hold time.


In the above figure, the shaded region is the restricted region. The shaded region is divided into two parts by the dashed line. The left hand side part of shaded region is the setup time period and the right hand side part is the hold time period. If the data changes in this region, as shown the figure. The output may, follow the input, or many not follow the input, or may go to metastable state (where output cannot be recognized as either logic low or logic high, the entire process is known as metastability).


The above figure shows the restricted region (shaded region) for a flip-flop whose hold time is negative. The following diagram illustrates the restricted region of a D flip-flop. D is the input, Q is the output, and clock is the clock signal. If D changes in the restricted region, the flip-flop may not behave as expected, means Q is unpredictable.


To avoid setup time violations:
  • The combinational logic between the flip-flops should be optimized to get minimum delay.
  • Redesign the flip-flops to get lesser setup time.
  • Tweak launch flip-flop to have better slew at the clock pin, this will make launch flip-flop to be fast there by helping fixing setup violations.
  • Play with clock skew (useful skews).
To avoid hold time violations:
  • By adding delays (using buffers).
  • One can add lockup-latches (in cases where the hold time requirement is very huge, basically to avoid data slip).
* may be expected one: which means output is not sure, it may be the one you expect. You can also say "may not be expected one". "may" implies uncertainty. Thanks for the readers for their comments.

Comments

In Sign said…
Nice information about VLSI Design.Thank you for sharing this information...
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Amaya said…
The Explanation of JK Flip Flop with its truth table would be very much appreciable :)

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