Most Common Interview Questions: Type-3: Give Verilog/VHDL code ...
The prime intention of the interviewer in asking this question is to see the hands-on experience you have. If you have mentioned that you are familiar with Verilog/VHDL in your resume and attending an ASIC engineer post, then you can expect this question. This question usually comes after asking Type-1 and/or Type-2 questions (explained in previous posts). No interviewer starts with this type of question.
The common strategy followed is: initially you will be asked "Type-1: Design a ..." and then as an extension you will be asked to code it in Verilog or VHDL. Further, the interviewer may specifically ask you, to code for synthesis.
- This question is asked to test your ability to code. Don't ever write a psuedo code or a code with syntax error(s).
- Prepare for this question by coding some basic programs like flip-flops, counters, small FSMs etc. Make sure that you touch most of the commonly used Verilog/VHDL keywords.
- Once you write some code, try to synthesize it and also try to find out the solution(s) if there are any errors.
- Code some combinational and sequential codes. Try to code using hierarchies.
You might also want to read the following articles
Type-2: Tell us about a design/project you worked on
Type-1: Design a ...
First Things First -- Preparing a Good Resume