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VLSI Interview Questions with Answers - 1

May 25, 2009

1. Why does the present VLSI circuits use MOSFETs instead of BJTs?
Answer

Compared to BJTs, MOSFETs can be made very small as they occupy very small silicon area on IC chip and are relatively simple in terms of manufacturing. Moreover digital and memory ICs can be implemented with circuits that use only MOSFETs i.e. no resistors, diodes, etc.

2. What are the various regions of operation of MOSFET? How are those regions used?
Answer

MOSFET has three regions of operation: the cut-off region, the triode region, and the saturation region.
The cut-off region and the triode region are used to operate as switch. The saturation region is used to operate as amplifier.

3. What is threshold voltage?
Answer

The value of voltage between Gate and Source i.e. V_GS at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called threshold voltage (V_t is positive for NMOS and negative for PMOS).

4. What does it mean "the channel is pinched off"?
Answer

For a MOSFET when V_GS is greater than V_t, a channel is induced. As we increase V_DS current starts flowing from Drain to Source (triode region). When we further increase V_DS, till the voltage between gate and channel at the drain end to become V_t, i.e. V_GS - V_DS = V_t, the channel depth at Drain end decreases almost to zero, and the channel is said to be pinched off. This is where a MOSFET enters saturation region.

5. Explain the three regions of operation of a MOSFET.
Answer

Cut-off region: When V_GS < V_t, no channel is induced and the MOSFET will be in cut-off region. No current flows.
Triode region: When V_GS ≥ V_t, a channel will be induced and current starts flowing if V_DS > 0. MOSFET will be in triode region as long as V_DS < V_GS - V_t.
Saturation region: When V_GS ≥ V_t, and V_DS ≥ V_GS - V_t, the channel will be in saturation mode, where the current value saturates. There will be little or no effect on MOSFET when V_DS is further increased.

6. What is channel-length modulation?
Answer

In practice, when V_DS is further increased beyond saturation point, it does has some effect on the characteristics of the MOSFET. When V_DS is increased the channel pinch-off point starts moving away from the Drain and towards the Source. Due to which the effective channel length decreases, and this phenomenon is called as Channel Length Modulation.

7. Explain depletion region.
Answer

When a positive voltage is applied across Gate, it causes the free holes (positive charge) to be repelled from the region of substrate under the Gate (the channel region). When these holes are pushed down the substrate they leave behind a carrier-depletion region.

8. What is body effect?
Answer

Usually, in an integrated circuit there will be several MOSFETs and in order to maintain cut-off condition for all MOSFETs the body substrate is connected to the most negative power supply (in case of PMOS most positive power supply). Which causes a reverse bias voltage between source and body that effects the transistor operation, by widening the depletion region. The widened depletion region will result in the reduction of channel depth. To restore the channel depth to its normal depth the VGS has to be increased. This is effectively seen as change in the threshold voltage - V_t. This effect, which is caused by applying some voltage to body is known as body effect.

9. Give various factors on which threshold voltage depends.
Answer

As discussed in the above question, the V_t depends on the voltage connected to the Body terminal. It also depends on the temperature, the magnitude of V_t decreases by about 2mV for every 1^oC rise in temperature.

10. Give the Cross-sectional diagram of the CMOS.
Answer

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June 22, 2019 at 6:52 AM

Digital Design Interview Questions - All in 1

January 20, 2009

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)? Answer 2. Implement an 2-input AND gate using a 2x1 mux. Answer 3. What is a multiplexer? Answer A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output. 4. What is a ring counter? Answer A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on. 5. Compare and Contrast Synchronous and Asynchronous reset. Answer Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for sma...

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223 comments

XMR: Cross Module Reference

September 12, 2017

Cross Module Reference Cross Module Reference abbreviated as XMR is a very useful concept in Verilog HDL (as well as system Verilog). However it seems to be less known among many users of Verilog. XMR is a mechanism built into Verilog to globally reference (i.e., across the modules) to any nets, tasks, functions etc. Using XMR, one can refer to any object of a module in any other module, irrespective of whether they are present below or above its hierarchy. Hence, a XMR can be a: Downward reference OR Upward reference Consider the following hierarchy: Module A Net x Instance P of Module B Net x Instance M of Module D Net x Instance Q of Module C Net x Instance N of Module E Net x Instance R of Module B Net x Instance M of Module D Net x ...

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One-hot Encoding

June 09, 2008

Designing a FSM is the most common and challenging task for every digital logic designer. One of the key factors for optimizing a FSM design is the choice of state coding, which influences the complexity of the logic functions, the hardware costs of the circuits, timing issues, power usage, etc. There are several options like binary encoding, gray encoding, one-hot encoding, etc. The choice of the designer depends on the factors like technology, design specifications, etc. One-hot encoding In one-hot encoding only one bit of the state vector is asserted for any given state. All other state bits are zero. Thus if there are n states then n state flip-flops are required. As only one bit remains logic high and rest are logic low, it is called as One-hot encoding. Example : If there is a FSM, which has 5 states. Then 5 flip-flops are required to implement the FSM using one-hot encoding. The states will have the following values: S0 - 10000 S1 - 01000 S2 - 00100 S3 - 00010 S4 - 00001 Adv...