1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)?

2. Implement an 2-input AND gate using a 2x1 mux.

3. What is a multiplexer?

4. What is a ring counter?

5. Compare and Contrast Synchronous and Asynchronous reset.

6. What is a Johnson counter?

7. An assembly line has 3 fail safe sensors and one emergency shutdown switch.The line should keep moving unless any of the following conditions arise:
(1) If the emergency switch is pressed
(2) If the senor1 and sensor2 are activated at the same time.
(3) If sensor 2 and sensor3 are activated at the same time.
(4) If all the sensors are activated at the same time
Suppose a combinational circuit for above case is to be implemented only with NAND Gates. How many minimum number of 2 input NAND gates are required?

8. In a 4-bit Johnson counter How many unused states are present?

9. Design a 3 input NAND gate using minimum number of 2 input NAND gates.

10. How can you convert a JK flip-flop to a D flip-flop?

11. What are the differences between a flip-flop and a latch?

12. What is the difference between Mealy and Moore FSM?

13. What are various types of state encoding techniques? Explain them.

14. Define Clock Skew , Negative Clock Skew, Positive Clock Skew.

15. Give the transistor level circuit of a CMOS NAND gate.

16. Design a 4-bit comparator circuit.

17. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR (without inverting the output)?

18. Define Metastability.

19. Compare and contrast between 1's complement and 2's complement notation.

20. Give the transistor level circuit of CMOS, nMOS, pMOS, and TTL inverter gate.

21. What are set up time and hold time constraints?

22. Give a circuit to divide frequency of clock cycle by two.

23. Design a divide-by-3 sequential circuit with 50% duty circle.

24. Explain different types of adder circuits.

25. Give two ways of converting a two input NAND gate to an inverter.

26. Draw a Transmission Gate-based D-Latch.

27. Design a FSM which detects the sequence 10101 from a serial line without overlapping.

28. Design a FSM which detects the sequence 10101 from a serial line with overlapping.

29. Give the design of 8x1 multiplexer using 2x1 multiplexers.

30. Design a counter which counts from 1 to 10 ( Resets to 1, after 10 ).

31. Design 2 input AND, OR, and EXOR gates using 2 input NAND gate.

32. Design a circuit which doubles the frequency of a given input clock signal.

33. Implement a D-latch using 2x1 multiplexer(s).

34. Give the excitation table of a JK flip-flop.

35. Give the Binary, Hexadecimal, BCD, and Excess-3 code for decimal 14.

36. What is race condition?

37. Give 1's and 2's complement of 19.

38. Design a 3:6 decoder.

39. If A*B=C and C*A=B then, what is the Boolean operator * ?

40. Design a 3 bit Gray Counter.

41. Expand the following: PLA, PAL, CPLD, FPGA.

42. Implement the functions: X = A'BC + ABC + A'B'C' and Y = ABC + AB'C using a PLA.

43. What are PLA and PAL? Give the differences between them.

44. What is LUT?

45. What is the significance of FPGAs in modern day electronics? (Applications of FPGA.)

46. What are the differences between CPLD and FPGA.

47. Compare and contrast FPGA and ASIC digital designing.

48. Give True or False.
(a) CPLD consumes less power per gate when compared to FPGA.
(b) CPLD has more complexity than FPGA
(c) FPGA design is slower than corresponding ASIC design.
(d) FPGA can be used to verify the design before making a ASIC.
(e) PALs have programmable OR plane.
(f) FPGA designs are cheaper than corresponding ASIC, irrespective of design complexity.

49. Arrange the following in the increasing order of their complexity: FPGA,PLA,CPLD,PAL.

50. Give the FPGA digital design cycle.

51. What is DeMorgan's theorem?

52. F'(A, B, C, D) = C'D + ABC' + ABCD + D. Express F in Product of Sum form.

53. How many squares/cells will be present in the k-map of F(A, B, C)?

54. Simplify F(A, B, C, D) = S ( 0, 1, 4, 5, 7, 8, 9, 12, 13)

55. Simplify F(A, B, C) = S (0, 2, 4, 5, 6) into Product of Sums.

56. The simplified expression obtained by using k-map method is unique. True or False. Explain your answer.

57. Give the characteristic tables of RS, JK, D and T flip-flops.

58. Give excitation tables of RS, JK, D and T flip-flops.

59. Design a BCD counter with JK flip-flops

60. Design a counter with the following binary sequence 0, 1, 9, 3, 2, 8, 4 and repeat. Use T flip-flops.

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### Setup and Hold TIme

Every flip-flop has restrictive time regions around the active clock edge in which input should not change. We call them restrictive because any change in the input in this regions the output may be the expected one (*see below). It may be derived from either the old input, the new input, or even in between the two. Here we define, two very important terms in the digital clocking. Setup and Hold time.
The setup time is the interval before the clock where the data must be held stable.The hold time is the interval after the clock where the data must be held stable. Hold time can be negative, which means the data can change slightly before the clock edge and still be properly captured. Most of the current day flip-flops has zero or negative hold time.

In the above figure, the shaded region is the restricted region. The shaded region is divided into two parts by the dashed line. The left hand side part of shaded region is the setup time period and the right hand side part is the hold time…

### Gate-Level Modeling

>> Introduction
>> Gate Primitives
>> Delays
>> Examples

Introduction

In Verilog HDL a module can be defined using various levels of abstraction. There are four levels of abstraction in verilog. They are:
Behavioral or algorithmic level: This is the highest level of abstraction. A module can be implemented in terms of the design algorithm. The designer no need to have any knowledge of hardware implementation.Data flow level: In this level the module is designed by specifying the data flow. Designer must how data flows between various registers of the design.Gate level: The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design.Switch level: This is the lowest level of abstraction. The design is implemented using switches/transistors. Designer requires the knowledge of switch-level implementation details.
Gate-level modeling is virtually the lowest-level of abstraction, because t…