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Digital Design Interview Questions - All in 1

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)?
Answer

2. Implement an 2-input AND gate using a 2x1 mux.
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3. What is a multiplexer?
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4. What is a ring counter?
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5. Compare and Contrast Synchronous and Asynchronous reset.
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6. What is a Johnson counter?
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7. An assembly line has 3 fail safe sensors and one emergency shutdown switch.The line should keep moving unless any of the following conditions arise:
(1) If the emergency switch is pressed
(2) If the senor1 and sensor2 are activated at the same time.
(3) If sensor 2 and sensor3 are activated at the same time.
(4) If all the sensors are activated at the same time
Suppose a combinational circuit for above case is to be implemented only with NAND Gates. How many minimum number of 2 input NAND gates are required?
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8. In a 4-bit Johnson counter How many unused states are present?
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9. Design a 3 input NAND gate using minimum number of 2 input NAND gates.
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10. How can you convert a JK flip-flop to a D flip-flop?
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11. What are the differences between a flip-flop and a latch?
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12. What is the difference between Mealy and Moore FSM?
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13. What are various types of state encoding techniques? Explain them.
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14. Define Clock Skew , Negative Clock Skew, Positive Clock Skew.
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15. Give the transistor level circuit of a CMOS NAND gate.
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16. Design a 4-bit comparator circuit.
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17. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR (without inverting the output)?
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18. Define Metastability.
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19. Compare and contrast between 1's complement and 2's complement notation.
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20. Give the transistor level circuit of CMOS, nMOS, pMOS, and TTL inverter gate.
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21. What are set up time and hold time constraints?
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22. Give a circuit to divide frequency of clock cycle by two.
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23. Design a divide-by-3 sequential circuit with 50% duty circle.
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24. Explain different types of adder circuits.
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25. Give two ways of converting a two input NAND gate to an inverter.
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26. Draw a Transmission Gate-based D-Latch.
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27. Design a FSM which detects the sequence 10101 from a serial line without overlapping.
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28. Design a FSM which detects the sequence 10101 from a serial line with overlapping.
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29. Give the design of 8x1 multiplexer using 2x1 multiplexers.
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30. Design a counter which counts from 1 to 10 ( Resets to 1, after 10 ).
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31. Design 2 input AND, OR, and EXOR gates using 2 input NAND gate.
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32. Design a circuit which doubles the frequency of a given input clock signal.
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33. Implement a D-latch using 2x1 multiplexer(s).
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34. Give the excitation table of a JK flip-flop.
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35. Give the Binary, Hexadecimal, BCD, and Excess-3 code for decimal 14.
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36. What is race condition?
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37. Give 1's and 2's complement of 19.
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38. Design a 3:6 decoder.
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39. If A*B=C and C*A=B then, what is the Boolean operator * ?
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40. Design a 3 bit Gray Counter.
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41. Expand the following: PLA, PAL, CPLD, FPGA.
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42. Implement the functions: X = A'BC + ABC + A'B'C' and Y = ABC + AB'C using a PLA.
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43. What are PLA and PAL? Give the differences between them.
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44. What is LUT?
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45. What is the significance of FPGAs in modern day electronics? (Applications of FPGA.)
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46. What are the differences between CPLD and FPGA.
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47. Compare and contrast FPGA and ASIC digital designing.
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48. Give True or False.
(a) CPLD consumes less power per gate when compared to FPGA.
(b) CPLD has more complexity than FPGA
(c) FPGA design is slower than corresponding ASIC design.
(d) FPGA can be used to verify the design before making a ASIC.
(e) PALs have programmable OR plane.
(f) FPGA designs are cheaper than corresponding ASIC, irrespective of design complexity.
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49. Arrange the following in the increasing order of their complexity: FPGA,PLA,CPLD,PAL.
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50. Give the FPGA digital design cycle.
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51. What is DeMorgan's theorem?
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52. F'(A, B, C, D) = C'D + ABC' + ABCD + D. Express F in Product of Sum form.
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53. How many squares/cells will be present in the k-map of F(A, B, C)?
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54. Simplify F(A, B, C, D) = S ( 0, 1, 4, 5, 7, 8, 9, 12, 13)
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55. Simplify F(A, B, C) = S (0, 2, 4, 5, 6) into Product of Sums.
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56. The simplified expression obtained by using k-map method is unique. True or False. Explain your answer.
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57. Give the characteristic tables of RS, JK, D and T flip-flops.
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58. Give excitation tables of RS, JK, D and T flip-flops.
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59. Design a BCD counter with JK flip-flops
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60. Design a counter with the following binary sequence 0, 1, 9, 3, 2, 8, 4 and repeat. Use T flip-flops.
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Comments

sunitha vishnu said…
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